A four quadrant high-speed CMOS analog multiplier based on the flipped voltage follower cell

Díaz-Sánchez, A.; Mateus-Ardila, Juan Carlos; Zamora-Mejia, Gregorio; Diaz-Armendariz, Alejandra; Rocha-Pérez, José Miguel; Moreno-Coria, Luis Armando

doi:10.1016/j.aeue.2020.153582

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Cited by 6 publications

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“…With improvement of integrated circuit, the high-speed application has been attracted great attention [7][8][9]. However, conventional voltage-mode circuit has a serious problem that the stray capacitance and parasitic capacitance limited the working frequency.…”

Section: Introductionmentioning

confidence: 99%

A 1 V, 10 KS/S, 71.2 db SNDR current-mode CMOS sample-and-hold circuit for high-speed wireless communication applications

Gao

Cai

et al. 2022

Preprint

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The sample and hold circuit has the function of collecting the analog input signal at a moment and maintaining its value. This article presents a current-mode sample and hold circuit for high-speed wireless communication applications. In this circuit, a single amplifier and a negative feedback structure are combined to eliminate the clock-feed through noise by using a virtual switch, and a differential structure is used to reduce the distortion caused by channel charge injection. This architecture achieves 71.2 db SNDR (signal to noise ratio plus distortion ratio) with a sampling rate of 10 KS/S when the power supply voltage is 1 V. The design of the sample and hold circuit is verified by the post-layout simulation of the standard 0.18 um CMOS technology.

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Section: Introductionmentioning

confidence: 99%