A 1 V, 10 KS/S, 71.2 db SNDR current-mode CMOS sample-and-hold circuit for high-speed wireless communication applications

Abstract

The sample and hold circuit has the function of collecting the analog input signal at a moment and maintaining its value. This article presents a current-mode sample and hold circuit for high-speed wireless communication applications. In this circuit, a single amplifier and a negative feedback structure are combined to eliminate the clock-feed through noise by using a virtual switch, and a differential structure is used to reduce the distortion caused by channel charge injection. This architecture achieves 71.2 db SNDR (signal to noise ratio plus distortion ratio) with a sampling rate of 10 KS/S when the power supply voltage is 1 V. The design of the sample and hold circuit is verified by the post-layout simulation of the standard 0.18 um CMOS technology.