A Four-Channel CMOS Front-End for Interference-Robust GNSS Receiver

Abstract

A four-channel receiver front-end is designed and implemented for interferenceand jamming-robust global navigation satellite system (GNSS) in a 0.18-µm CMOS technology. The front-end consists of four identical RF-to-IF signal paths including low-noise amplifiers (LNAs), mixers and IF amplifiers. In addition, it also includes a phase-locked loop (PLL), which synthesizes the local oscillator (LO) signal, and a serial peripheral interface (SPI) for parameter adjustment. To improve the interference and jamming robustness, a novel linearity improvement technology and LO duty cycle adjustment method are applied in LNA and mixer design, respectively. The receiver achieves a gain of 40 dB, an input-referred third-order intercept point (IIP3) of −8 dBm and a jammer-to-signal power ratio (JSR) of 72 dB under 1.8-V and 3.3-V supply, while occupying a 4 × 5 mm 2 die area including the electrostatic discharge (ESD) I/O pads.Electronics 2020, 9, 291 2 of 11 power of the signal is much lower than the interference or jammer, scaled by the jammer-to-signal power ratio (JSR). However, the JSR in [4] remains to be improved.This manuscript describes the design and implementation of a four-channel GNSS front-end in a 0.18-µm standard CMOS process with a new linearity improvement technique applied in the low-noise amplifier (LNA) and with a novel local oscillator (LO) duty cycle adjustment method for a voltage-driven passive mixer in order to obtain better performance under strong in-band interference and jamming. Section 2 begins with describing the architecture and system design consideration of the front-end. Section 3 then presents the circuit implementations in detail. Experimental results are provided in Section 4, and the manuscript concludes with a summary in Section 5. System ArchitectureA detailed block diagram of the four-channel CMOS GNSS receiver is shown in Figure 1. Each channel of the RF front-end is composed of an off-chip LNA (modeling the GaAs LNA in the antenna), an off-chip Balun, an on-chip LNA, an off-chip image-rejection filter, a down-conversion mixer and an IF amplifier (IFA). Two-stage LNA, mixer, IFA of four channels and a PLL are integrated on a single chip. The received RF signal is first amplified by the two-stage LNA. After filtering by the image-rejection filter, the signal is down-converted to the IF frequency by the mixer and then amplified by the IFA. The output of the IFA is capable of driving an ADC with high input impedance. PLL provides four-channel LO signals for down-conversion. The bandgap reference (BGR) is applied for independent bias current and voltage required by each module of the system. Parameter adjustment is achieved by the SPI. An off-chip filter for image rejection of the RF band is employed for each channel, since an on-chip filter with such high image rejection ratio while meeting a bandwidth requirement can hardly be implemented for the specific application. The input impedance and output impedance are both matching to 100 Ω.

Design and Verification of a Charge Pump in Local Oscillator for 5G Applications

“…A phase-locked loop (PLL)-based frequency synthesizer is a vital component in communication systems [1,2]. To support the high data-rate transmission in 5G systems, the stringent requirements of being both fast settling with low power consumption must be satisfied.…”