A Flow Analysis Procedure for the Translation of High-Level Languages to a Data Flow Language

Allan,; Oldehoeft,

doi:10.1109/tc.1980.1675682

Cited by 29 publications

(8 citation statements)

References 6 publications

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“…The results are shown in Table 2 below, where program EVEN is the example in Figure 9, COND. is a nested if-expression from [22], RAND is a simple (additive) random number generator taken from [23] (p.26), and RUNGE is the Runge-Kutta program in [24]. Shown in the Table are From the Table we observe again that the average path length remains almost constant for all the programs, even though the array utilization varies significantly.…”

Section: Performance Of the Mapping Processmentioning

confidence: 89%

Mapping data flow programs on a VLSI array of processors

Mendelson

Silberman

1987

Proceedings of the 14th Annual International Symposium on Computer Architecture - ISCA '87

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With the advent of VLSI, relatively large processing arrays may be realized in a single VLSI chip. Such regularly structured arrays take considerably less time to design and test, and fault-tolerance can easily be introduced into them. However, only a few computational algorithms which can effectively use such regular arrays have been developed so far.We present an approach to mapping arbitrary algorithms, expressed as programs in a data flow language, onto a regular array of data-driven processors implemented by a number of VLSI chips. Each chip contains a number of processors, interconnected by a set of regular paths, and connected to processors in other similar chips to form a large array. This array is thus tailored to perform a specific computational task, as an attached processor in a larger system.The data flow program is first translated into a graph representation, the dataflow graph, which is then mapped onto a finite but (theoretically) unbounded array of identical processors. Each node in the graph represents an operation which can be performed by an individual processor in the array. Therefore, the mapping operation consists of assigning nodes in the graph to processors in the array, and defining the connections between the processors according to the arcs in the graph. The last step consists of partitioning the unbounded array into a number of segments, to account for the number of processors which fit in a single VLSI chip.

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Section: Performance Of the Mapping Processmentioning

confidence: 89%

Mapping data flow programs on a VLSI array of processors

Mendelson

Silberman

1987

Proceedings of the 14th Annual International Symposium on Computer Architecture - ISCA '87

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“…WaveScalar provides a memory interface called waveordered memory (described in [5]) that enables it to execute programs written in imperative languages (such as C, C++, or Java [6,25]), by providing the well-ordered memory semantics these languages require.…”

Section: Wave-ordered Interfacementioning

confidence: 99%

Area-Performance Trade-offs in Tiled Dataflow Architectures

Swanson

Putnam

Mercaldi

et al. 2006

SIGARCH Comput. Archit. News

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Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and performance. The basic premise of these architectures is that larger, higher-performance implementations can be constructed by replicating the basic tile across the chip.This paper explores the area-performance trade-offs when designing one such tiled architecture, WaveScalar. We use a synthesizable RTL model and cycle-level simulator to perform an area/performance pareto analysis of over 200 WaveScalar processor designs ranging in size from 19mm 2 to 378mm 2 and having a 22 FO4 cycle time. We demonstrate that, for multi-threaded workloads, WaveScalar performance scales almost ideally from 19 to 101mm 2 when optimized for area efficiency and from 44 to 202mm 2 when optimized for peak performance. Our analysis reveals that WaveScalar's hierarchical interconnect plays an important role in overall scalability, and that WaveScalar achieves the same (or higher) performance in substantially less area than either an aggressive out-of-order superscalar or Sun's Niagara CMP processor.

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“…Moreover, it supports easier program verification, enhancing the clarity of programs, and increasing programmer productivity [4].…”

Section: Dataf Lo W Lan Gua Ge Smentioning

confidence: 99%