Area-Performance Trade-offs in Tiled Dataflow Architectures

Abstract

Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and performance. The basic premise of these architectures is that larger, higher-performance implementations can be constructed by replicating the basic tile across the chip.This paper explores the area-performance trade-offs when designing one such tiled architecture, WaveScalar. We use a synthesizable RTL model and cycle-level simulator to perform an area/performance pareto analysis of over 200 WaveScalar processor designs ranging in size from 19mm 2 to 378mm 2 and having a 22 FO4 cycle time. We demonstrate that, for multi-threaded workloads, WaveScalar performance scales almost ideally from 19 to 101mm 2 when optimized for area efficiency and from 44 to 202mm 2 when optimized for peak performance. Our analysis reveals that WaveScalar's hierarchical interconnect plays an important role in overall scalability, and that WaveScalar achieves the same (or higher) performance in substantially less area than either an aggressive out-of-order superscalar or Sun's Niagara CMP processor.

Verilog-based simulation of hardware support for data-flow concurrency on multicore systems

“…The TRIPS architecture [21], [20] is an instantiation of an EDGE ISA which utilizes large cores consisting of a matrix of execution units. In [22], the authors explore the area-performance trade-offs of a tiled data-flow architecture. A tiled architecture promises to address several issues facing conventional processors, such as complexity and performance.…”

Implementation and Evaluation of a Dynamically Routed Processor Operand Network

“…The WaveScalar processor has a similar philosophy and execution model as TRIPS, but uses a hierarchy of interconnection networks to pass operands between processing elements [9]. Operands are broadcast within the eight processing elements making up one domain.…”

Instruction scheduling for a tiled dataflow architecture

“…We scheduled nine sample applications from the Spec2000 [35] and Splash2 [4] benchmark suites (art, equake, gzip, mcf, radix, twolf and fft, lu, ocean, respectively). 2 The cycle-level simulator used for this study is tuned to match the latencies, resources, and restrictions of an RTL implementation [37] of the architecture. Table 2 shows the average performance of each of these nine schedules.…”

“…A simple PE decreases both design and verification time; PE replication provides robustness in the face of fabrication errors; and the combination reduces wire delay for both data and control signal transmission. The result is a scalable architecture that allows a chip designer to target different levels of performance, with different area budgets [37].…”