A Floating CDAC architecture for high-resolution and low-power SAR A/D converter

Wickmann, Andreas; Ohnhäuser, Frank

doi:10.1109/iscdg.2012.6360003

Cited by 3 publications

(3 citation statements)

References 2 publications

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“…However, reliability issue arises as the input voltage of comparator exceeds its supply voltage or below 0 during the first few bit cycles. In [14], a floating CDAC technique is proposed to reduce the input swing during the first few bit cycles by floating some CDAC input. In the following bit cycles, the sampled charge of the floating CDAC is released and the conversion runs with the highest precision.…”

Section: Two Branches Floating Cdac Schemementioning

confidence: 99%

“…In this work, a 16 bit 1‐MS/s SAR ADC is implemented with foreground digital‐domain calibration for CDAC mismatch errors. A

V_{cm}

‐free technique is proposed to eliminate the power hungry

V_{cm}

generator, and a floating CDAC scheme [14] is adopted to achieve high input signal range under a low core supply voltage. Besides, a modified direct‐switching CDAC SAR logic is proposed to speed up SAR ADC.…”

Section: Introductionmentioning

confidence: 99%

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16‐bit 1‐MS/s SAR ADC with foreground digital‐domain calibration

Guan

Xue

Yang

et al. 2018

IET Circuits, Devices & Systems

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This study presents a low-power 16-bit 1-MS/s successive approximation register analogue-to-digital converter (SAR ADC) for medical instrument applications. A foreground digital-domain calibration method simultaneously correcting mismatch errors in capacitive digital-to-analogue converter (CDAC) and 'segment error' of split-CDAC array is proposed. The split-CDAC architecture combines a V cm-free technique in a floating CDAC scheme. The V cm-free technique avoids a power hungry V cm generator, and the floating CDAC scheme allows the conversion of a high-voltage input signal with low supply voltage and without a significant attenuation of the input signal. Moreover, a modified direct-switching SAR logic is adopted to improve the conversion speed. The prototype was fabricated in a 0.18 µm 1P6M Complementary Metal Oxide Semiconductor (CMOS) technology, and achieves 86.16 dB signal-to-noise and distortion ratio and an Figure of Merit (FOM) of 0.41 pJ/conversion-step.

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Section: Two Branches Floating Cdac Schemementioning

confidence: 99%

“…In this work, a 16 bit 1‐MS/s SAR ADC is implemented with foreground digital‐domain calibration for CDAC mismatch errors. A

V_{cm}

‐free technique is proposed to eliminate the power hungry

V_{cm}

Section: Introductionmentioning

confidence: 99%

16‐bit 1‐MS/s SAR ADC with foreground digital‐domain calibration

Guan

Xue

Yang

et al. 2018

IET Circuits, Devices & Systems

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“…S UCCESSIVE approximation register analog-to-digital converters (SAR ADCs) are used in medium-resolution and medium-speed applications, such as motor control, battery monitoring, touch-screen control, and other sensor interfaces, requiring low latency, monotonicity, and low quiescent power consumption [1]- [6]. A high-voltage (HV) input range operation is enabled by directly sampling on the bottom plate of the capacitor array to achieve higher input impedance at a lower operating frequency specifically for industrial motor control applications [7]. In conventional high-performance S. Thirunakkarasu is with RF Mixed Signal Group, Broadcom Corporation, Austin, TX 78746 USA (e-mail: shankart@broadcom.com).…”

Section: Introductionmentioning

confidence: 99%

Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL

Thirunakkarasu

Bakkaloglu

2015

IEEE Trans. VLSI Syst.

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Several state-of-the-art monitoring and control systems, such as dc motor controllers, power line monitoring and protection systems, instrumentation systems, and battery monitors, require direct digitization of high-voltage (HV) input signals. Analog-to-digital converters (ADCs) that can digitize HV signals require high linearity and low-voltage coefficient capacitors. A built-in self-calibration and digital-trim algorithm correcting static mismatches in capacitive digital-to-analog converter (DAC) used in successive approximation register analog-todigital converters (SAR ADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit HV input range SAR ADC with integrated DEC capacitors. The IC is fabricated in 0.6-µm HV-compliant CMOS process, accepting up to 24V pp differential input signal. The proposed approach achieves 73.32-dB signal-to-noise and distortion ratio, which is an improvement of 12.03 dB after self-calibration at 400-kS/s sampling rate, consuming 90 mW from a ±15 V supply. The calibration circuitry occupies 28% of the capacitor DAC and consumes <15 mW during operation. Measurement results show that this algorithm reduces integral nonlinearity from as high as 7 LSBs down to 1 LSB, and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces differential nonlinearity errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm 2 .

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