16‐bit 1‐MS/s SAR ADC with foreground digital‐domain calibration

Abstract

This study presents a low-power 16-bit 1-MS/s successive approximation register analogue-to-digital converter (SAR ADC) for medical instrument applications. A foreground digital-domain calibration method simultaneously correcting mismatch errors in capacitive digital-to-analogue converter (CDAC) and 'segment error' of split-CDAC array is proposed. The split-CDAC architecture combines a V cm-free technique in a floating CDAC scheme. The V cm-free technique avoids a power hungry V cm generator, and the floating CDAC scheme allows the conversion of a high-voltage input signal with low supply voltage and without a significant attenuation of the input signal. Moreover, a modified direct-switching SAR logic is adopted to improve the conversion speed. The prototype was fabricated in a 0.18 µm 1P6M Complementary Metal Oxide Semiconductor (CMOS) technology, and achieves 86.16 dB signal-to-noise and distortion ratio and an Figure of Merit (FOM) of 0.41 pJ/conversion-step.

Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

“…It can be seen from Fig. 2 that for the 16-bit ADC, the total number of unit capacitors is 2 16 = 65536, and the layout area is too large to achieve. Set the number of unit capacitors used in the N-th weight capacitor to Num(N).…”

“…For the SAR capacitor array shown in Fig. 3, to ensure that the capacitor array meets the 16-bit conversion accuracy, it is necessary to ensure that the relative error of all capacitors is less than 1/2 16 . By consulting the current major IC foundry, it can be known that the current natural matching accuracy of the capacitor is about 10 bits, that is, the relative error of the capacitor is larger than 1/2 10 , and all capacitors are required to be unit capacitors.…”

“…It can be easily derived from Equation (4) and Equation (3): BIT(1)∼BIT(11) meet the requirement of Equation (3). When BIT(11) meets the requirement of Equation (3), it can be concluded that BIT(1)∼BIT (16) all meet the requirements of Equation (3).…”

“…9, the IC foundry can only provide 10bit matching accuracy, and the bridge capacitor B2 is a nonunit capacitor. The weight capacitors of BIT(11)∼BIT (16) will have an obvious mismatch, and the Cal(N) unit will compensate for the mismatch of the corresponding capacitor.…”

“…Although the mismatch is small, it is known through theoretical analysis that SNR will not show a large deviation. However, there will be significant differences of the DNL values of BIT(6), BIT(10), BIT(11), and BIT (16). Therefore, in the simulation, we will focus on comparing the DNL parameters.…”