A flexible ultra-thin-body SOI single-photon avalanche diode

Sun, Pengfei; Mimoun, B.; Charbon, Edoardo; Ishihara, Ryoichi

doi:10.1109/iedm.2013.6724606

Cited by 6 publications

(9 citation statements)

References 8 publications

(6 reference statements)

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“…Thanks to the buffering circuits, the dead time, which depends on RC recharge time in a passive quenching scheme, was reduced to around 160ns and consequently the PDP was enhanced because of the increased saturation frequency, which determines the upper limit of photon flux detectability. Furthermore, compared with our previous work [13], the PDP performance of BSI SPADs was also improved. The main reason is the epitaxy body doping diffusion into the intrinsic silicon layer on top of the buried oxide layer (Fig.…”

Section: Characteristics On Flexible Cmos Spad Sensor Pixelmentioning

confidence: 65%

“…1(a), a P + enhancement region is made to form the multiplication region, where the electric field is concentrated in this planar region and higher than that around the curvature region of the junction, thus preventing premature edge breakdown [18,19]. It has been confirmed by DCR versus temperature measurements [13] that a large portion of dark noise comes from band-to-band tunneling due to high doping in the multiplication region. DCR as a function of excess bias based on devices with different doping levels in the multiplication region is reported in Fig.…”

Section: Characteristics On Flexible Trench-isolated Spad Integrated mentioning

confidence: 70%

“…Compared with our previous work [13], the excess bias could be increased to 4V, by integrating CMOS buffering. The characterization of DCR as a function of excess bias is shown in Fig.…”

Section: Characteristics On Flexible Cmos Spad Sensor Pixelmentioning

confidence: 99%

“…It was fabricated by our previously proposed flexible ultrathin-body SPAD technology enabling dual-side illumination [12,13]. The SPAD was realized in circular shape based on a N + /P junction with P-type enrichment doping in the multiplication region.…”

Section: Device Structure and Fabrication Flowchartmentioning

confidence: 99%

“…However, current SPAD technology is generally implemented on bulk silicon and can't meet the requirements of implantable biomedical applications where backside-illumination and new substrate post processing are core technologies, while inherent CMOS compatibility is a requirement [10,11]. In our previous work, we demonstrated the world's first flexible SPAD fabricated in an ultrathin-body silicon-on-insulator (SOI) process followed by transfer post-processing to flexible substrate [12], and we achieved a flexible SPAD with dual-side illumination for the first time [13].…”

Section: Introductionmentioning

confidence: 99%

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Flexible ultrathin-body single-photon avalanche diode sensors and CMOS integration

Sun¹,

Ishihara²,

Charbon³

2016

Opt. Express

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Abstract:We proposed the world's first flexible ultrathin-body singlephoton avalanche diode (SPAD) as photon counting device providing a suitable solution to advanced implantable bio-compatible chronic medical monitoring, diagnostics and other applications. In this paper, we investigate the Geiger-mode performance of this flexible ultrathin-body SPAD comprehensively and we extend this work to the first flexible SPAD image sensor with in-pixel and off-pixel electronics integrated in CMOS. Experimental results show that dark count rate (DCR) by band-to-band tunneling can be reduced by optimizing multiplication doping. DCR by trap-assisted avalanche, which is believed to be originated from the trench etching process, could be further reduced, resulting in a DCR density of tens to hundreds of Hertz per micrometer square at cryogenic temperature. The influence of the trench etching process onto DCR is also proved by comparison with planar ultrathin-body SPAD structures without trench. Photon detection probability (PDP) can be achieved by wider depletion and drift regions and by carefully optimizing body thickness. PDP in frontside-(FSI) and backside-illumination (BSI) are comparable, thus making this technology suitable for both modes of illumination. Afterpulsing and crosstalk are negligible at 2µs dead time, while it has been proved, for the first time, that a CMOS SPAD pixel of this kind could work in a cryogenic environment. By appropriate choice of substrate, this technology is amenable to implantation for biocompatible photon-counting applications and wherever bended imaging sensors are essential.

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Section: Characteristics On Flexible Cmos Spad Sensor Pixelmentioning

confidence: 65%

Section: Characteristics On Flexible Trench-isolated Spad Integrated mentioning

confidence: 70%

“…Compared with our previous work [13], the excess bias could be increased to 4V, by integrating CMOS buffering. The characterization of DCR as a function of excess bias is shown in Fig.…”

Section: Characteristics On Flexible Cmos Spad Sensor Pixelmentioning

confidence: 99%

Section: Device Structure and Fabrication Flowchartmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Flexible ultrathin-body single-photon avalanche diode sensors and CMOS integration

Sun¹,

Ishihara²,

Charbon³

2016

Opt. Express

Self Cite

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Single-photon imaging in complementary metal oxide semiconductor processes

Charbon

2014

Phil. Trans. R. Soc. A.

129

100

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This paper describes the basics of single-photon counting in complementary metal oxide semiconductors, through single-photon avalanche diodes (SPADs), and the making of miniaturized pixels with photon-counting capability based on SPADs. Some applications, which may take advantage of SPAD image sensors, are outlined, such as fluorescence-based microscopy, three-dimensional time-of-flight imaging and biomedical imaging, to name just a few. The paper focuses on architectures that are best suited to those applications and the trade-offs they generate. In this context, architectures are described that efficiently collect the output of single pixels when designed in large arrays. Off-chip readout circuit requirements are described for a variety of applications in physics, medicine and the life sciences. Owing to the dynamic nature of SPADs, designs featuring a large number of SPADs require careful analysis of the target application for an optimal use of silicon real estate and of limited readout bandwidth. The paper also describes the main trade-offs involved in architecting such chips and the solutions adopted with focus on scalability and miniaturization.

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