A flexible interface architecture for reconfigurable coprocessors in embedded multicore systems using PCIe Single-root I/O virtualization

Abstract

Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a flexible interface architecture with low overhead for coupling reconfigurable coprocessors to highperformance general-purpose processors, allowing customized yet efficient construction of heterogeneous processing systems. Our implementation is based on PCI Express (PCIe) and optimized for virtualized systems, taking advantage of the SR-IOV capabilities in modern PCIe implementations. We describe the interface architecture and its fundamental technologies, detail the services provided to individual coprocessors and accelerator modules, and quantify key corner performance indicators relevant for virtualized applications.

Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization

“…Our implementation is based on previous works on a flexible interface architecture that provides a low-latency, highbandwidth and QoS-enabled link between an Intel multicore platform connected via PCIe to coprocessors implemented on a Xilinx Virtex-7 FPGA [2]. It covers the adaption of a standard PCIe SR-IOV interface on one side and a generic AXI interconnect [11] on the other side.…”

“…In the previous work without partial reconfiguration [2], each coprocessor always occupies a specific region of the FPGA and thus uses the same AXI connection to communicate with the PCIe-2-AXI Adapter. The mapping between PCIe Routing ID and the AXI connection, which is done by the adapter, remains the same.…”

“…Based on an interface architecture providing lowlatency register accesses and high-performance DMA transfers for individual coprocessors [2], our concept adds the flexible use of FPGA resources based on partial reconfiguration while either hiding its low-level details from non-critical software tasks or providing full control and predictable behavior for safety relevant ones. Our prototype implementation is based on PCI Express (PCIe), which is available in a multitude of platforms spanning most important application domains-from HPC to embedded-and all major processor architectures.…”

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors

“…It is also promising to integrate an FPGA as a heterogeneous core in an NoC-based multicore system as the next-generation heterogeneous system. Nevertheless, most prior research work has focused on the interfacing of off-chip FPGAs and processors [7], [8], [9], [10], [11] with a limited number of cores through bus-based communication. Moreover, the rapid increase in the resource capacity and variety of FPGAs over the past few years has made it feasible to implement multiple accelerators on a single FPGA.…”

UniLogic (unified logic)

“…This kind of frameworks [52], as well as relative commercial schemes such as the Coral [51] offered by InAccel, could take advantage of the UNILOGIC architecture, complementary offering a holistic approach for FPGA deployment. The work in [100], addresses the virtualization of hardware accelerators through the Single-Root I/O Virtualization feature of the PCI Express interface. The proposed system is capable of statically sharing predefined co-processors in a single FPGA among a host and several virtual machines; therefore, co-processors are not shareable between domains, while in [115] the system gets augmented with partial reconfiguration support.…”