Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization

Abstract

Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a concept that leverages the advantages of FPGA's partial reconfiguration in heterogeneous mixed criticality multicore systems. We describe the basic idea how to handle the partial reconfiguration transparently for non-critical tasks, while providing full control and a predictable behavior for safety relevant tasks. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express (PCIe), taking advantage of the Single-Root I/O Virtualization (SR-IOV) capabilities in modern PCIe implementations. Preliminary experimental results show that our concept achieves significantly shorter reconfiguration time with lower variance compared to other solutions.

Extra

“…We evaluated two accelerated image processing applications, which we combine to produce three execution scenarios: (a) multiple instances of a single application share all the accelerators, (b) multiple instances of both applications share the common accelerators, and (c) with multiple threads that do not share any of the hardware accelerators. Our results show that (1) despite its generality, RACOS can achieve high throughput rates, close to the maximum reported in bibliography [38], and (much) better reconfiguration throughput reaching 177 partial reconfigurations per second for our platform and benchmark accelerators, and (2) that RACOS' flexibility comes at a very small resource cost (about 3% of a medium sized FPGA), comparable or better than the current state of the art [39].…”

AvA: Accelerated Virtualization of Accelerators

“…The technique can provide strong virtualization guarantees [36,37], but hardware-level resource management is inflexible and unevolvable: current implementations are trivially vulnerable to fragmentation and unfairness pathologies that cannot be changed. Moreover, evidence is scant that broad SR-IOV support will emerge for accelerators: only two current GPUs support it [4,46], none of the TPUs we evaluate support it; and SR-IOV interface IP blocks from FPGA vendors (used by [47,76,96,108]) do not implement resource management. We do not expect this to change any time soon: SR-IOV requires significant engineering effort vendors are not incentivized to invest.…”

Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator

“…Although our approach addresses similar applications, our strategy prioritizes the maximum area reuse of RPs while reducing the number of reconfigurations on a PCIe-based FPGA. Despite the fact that none of the mentioned works uses PCIe, PR through PCIe has been already targeted in [17,18]. Our proposed NE presents a more complex application which benefits from the current state-of-the-art technology [19].…”

“…for ∈ RP do (8) for ∈ Size( ) do (9) if Config( temp ( )) = Config( ( )) then (10) node [ ] ← InsertConfigInRP( ( ), ); (11) node [ ] ← MarkAsConfigured(); (12) ← RemoveConfigfromList( , ); (13) break; (14) end (15) end (16) end (17) if…”