A Flexible Framework for Exploring, Evaluating, and Comparing SHA-2 Designs

Abstract

Hash functions are a crucial tool in a large variety of applications, ranging from security protocols to cryptocurrencies down to the Internet-of-Things devices used, for example, as biomedical appliances. In particular, SHA-2 is today a ubiquitous hashing primitive. Its acceleration has driven a wealth of contributions in the technical literature and even a whole industry segment involving dedicated hash processing accelerators. Because of the variety of requirements in terms of performance, resources, and energy consumption as well as the impact of the particular hardware technology of choice, evaluating and comparing different architectural schemes is a nontrivial task, along with the exploration of new solutions matching given user requirements. Based on a careful review of the state of the art, this paper introduces an SHA-2 workbench to be used as a framework for evaluating different implementation styles and architectural choices. The workbench comes in the form of a generic HDL description, where the various implementation options are exposed in the form of user-configurable parameters and can be variously combined obtaining either known solutions or possibly new configurations to be explored. We systematically use the workbench to analyze the available SHA-2 architectural techniques. This extensive evaluation provides a deep understanding of the performance and energy implications of each implementation style and even allows the identification of nonobvious matches between architectural choices and target technologies in order to optimize hash rate and area efficiency figures.

SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

“…On the other hand, loop unrolling can be expected to be beneficial, despite the area increase, due to its frequency and register operation reduction. The experimental evaluation of [2] confirms the impact of loop unrolling, while other techniques appear not to have significant effects on power consumption. Loop folding has in fact twofold implications on power consumption.…”

“…This implies that the overall effect of loop unrolling on throughput is technology-dependent. In [2] loop unrolling turns out to be beneficial for throughput on fairly recent FPGAs.…”

“…This paper comprehensively surveys the available techniques, discussing their impact on the different evaluation metrics of relevance for the designer: throughput, area occupation, and energy or power consumption. The discussion takes also advantage of the authors' previous work [2], which presented a SHA-2 evaluation framework used to analyze the implementation requirements of existing solutions. This analysis is combined here with an extensive review of the state of the art to systematically show how relevant evaluation metrics are affected by architectural choices.…”

Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining

“…To ensure a fair comparison with other existing SHA-256 architectures, such as [18], [19], [20], [21], [22], and [23], we synthesized the proposed CME double SHA-256 circuit on four Xilinx FPGA boards, including Kintex UltraScale (XCKU5P-ffva676-3-e), Virtex 7(XC7VX1140T-FLG1926-2), Artix 7 (XC7A200T-FBG484-1), and Zynq UltraScale+ ZCU102 (XCZU9EG-FFVB1156-2-e).…”

“…The authors of [17] used a combination of techniques such as carry-save-adders and pipelines to increase the performance of SHA-256. Pipeline and unrolled techniques are presented in [18] and [19] to increase the throughput of SHA-256. The authors of [20]- [22] presented a SHA-256 implementation on an FPGA for performance evaluation, with no technique optimization.…”