A first insight into object-aware hardware transactional memory

Khan, Behram; Horsnell, Matthew; Rogers, Ian; Luján, Mikel; Dinn, Andrew; Watson, Ian

doi:10.1145/1378533.1378552

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…To address the limitations of previously proposed object-based hardware transactional memory (HTM) system [4] [3], this paper presents a protocol capable of maintaining transactional execution over a scalable memory architecture. This section presents the SO protocol, which no longer relies on a network that supports atomic broadcasts but rather is extendible to function on any scalable network architecture.…”

Section: So Protocol Overviewmentioning

confidence: 99%

Scalable Object-Aware Hardware Transactional Memory

Khan

Horsnell

Luján

et al. 2010

Euro-Par 2010 - Parallel Processing

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A Hardware Transactional Memory (HTM) aids the construction of lock-free regions within applications with fewer concerns about correctness and potentially greater performance through optimistic concurrency. Object-aware hardware adds a level of indirection to memory accesses, memory addresses become a combination of the object being accessed and the offset within it. The hardware maintains a mapping from objects to memory locations just as a mapping from virtual to real memory is handled through page tables. In a scalable object-aware system the directories are addressed by objects identifiers.In this paper we extend a scalable object-aware memory system to implement a HTM. Our object-aware protocol permits locks on directories to be avoided for objects only read during a transaction. Working at the granularity of an object allows entries within the directories to be associated with multiple cache lines, as opposed to one, and reduce the amount of network traffic. Finally, our commit protocol dispenses with the need for a centrally controlled transaction ID order.

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Section: So Protocol Overviewmentioning

confidence: 99%

Scalable Object-Aware Hardware Transactional Memory

Khan

Horsnell

Luján

et al. 2010

Euro-Par 2010 - Parallel Processing

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Atomicity failure and the retrenchment atomicity pattern

Banach

Jeske

Hall³

et al. 2013

Form. Asp. Comput.

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Abstract. The issues surrounding the question of atomicity, both in the past and nowadays, are briefly reviewed, and a picture of an ACID (atomic, consistent, isolated, durable) transaction as a refinement problem is presented. An example of a simple air traffic control system is introduced, and the discrepancies that can arise when read-only operations examine the state at atomic and finegrained levels are handled by retrenchment. Non-ACID timing aspects of the ATC example are also handled by retrenchment, and the treatment is generalised to yield the Retrenchment Atomicity Pattern. The utility of the pattern is confirmed against a number of different case studies. One is the Mondex Electronic Purse, its protocol treated as a conventional atomic transaction. Another is the recovery protocol of Mondex, viewed as a compensated transaction (leading to the view that compensated transactions in general fit the pattern). A final one comprises various unruly phenomena occurring in the implementations of software transactional memory systems, which can frequently display non-ACID behaviour. In all cases the Atomicity Pattern is seen to perform well.

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Hardware Transactional Memories

Shahid

Murad

Qadri

et al. 2016

Innovative Research and Applications in Next-Generation High Performance Computing

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The initiation to have a concept of shared memory in processors has built an opportunity for thread level parallelism. In various applications, synchronization or ordering tools are utilized to have an access to shared data. Traditionally, multithreaded programming models usually suggest a set of low-level primitives, such as locks, to guarantee mutual exclusion. Possession of one or more locks protects access to shared data. But, due to some flaws they become a suboptimal solution. The idea of transactional memory is in research presently as an alternative to locks. Among which, one way is hardware transactional memory. Atomicity is well supported by using transactions in hardware. In this chapter, we have focused on hardware transactional memories and the work done on them so far.

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A first insight into object-aware hardware transactional memory

Cited by 3 publications

References 5 publications

Scalable Object-Aware Hardware Transactional Memory

Scalable Object-Aware Hardware Transactional Memory

Atomicity failure and the retrenchment atomicity pattern

Hardware Transactional Memories

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