A feature-based classification of formal verification techniques for software models

Gabmeyer, Sebastian; Kaufmann, Petra; Seidl, Martina; Gogolla, Martin; Kappel, Gerti

doi:10.1007/s10270-017-0591-z

Cited by 25 publications

(21 citation statements)

References 108 publications

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“…Verification ensures that the software is aligned with its desired requirements, meets particular necessities, completeness, and performance according to specifications [4]. It strives to fulfill consistency, the correctness of program translations as well as behavioral correctness [6]. Validation is the determination of the correctness of the software at every stage of the development cycle [5].…”

Section: Introductionmentioning

confidence: 99%

An efficient software verification using multi-layered software verification tool

Devi¹,

Nalini²,

Kumar³

2018

IJET

150

171

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Rapid advancements in Software Verification and Validation have been critical in the wide development of tools and techniques to identify potential Concurrent bugs and hence verify the software correctness. A concurrent program has multiple processes and shared objects. Each process is a sequential program and they use the shared objects for communication for completion of a task. The primary objective of this survey is retrospective review of different tools and methods used for the verification of real-time concurrent software. This paper describes the proposed tool 'F-JAVA' for multithreaded Java codebases in contrast with existing 'FRAMA-C' platform, which is dedicated to real-time concurrent C software analysis. The proposed system is comprised of three layers, namely Programming rules generation stage, Verification stage with Particle Swarm Optimization (PSO) algorithm, and Performance measurement stage. It aims to address some of the challenges in the verification process such as larger programs, long execution times, and false alarms or bugs, and platform independent code verification

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Section: Introductionmentioning

confidence: 99%

An efficient software verification using multi-layered software verification tool

Devi¹,

Nalini²,

Kumar³

2018

IJET

150

171

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“…In [39], Gabmeyer et al have proposed a taxonomy of formal verification techniques for software models. In this section, discussion focuses on recent papers addressing simulation and formal verification in the context of SysML.…”

Section: B Formal Verification Of Sysml Modelsmentioning

confidence: 99%

An Educational Case Study of Using SysML and TTool for Unmanned Aerial Vehicles Design

Apvrille

Saqui-Sannes

Vingerhoeds

2020

IEEE J. Miniat. Air Space Syst.

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The paper shares an experience in using the Systems Modeling Language (SysML) for the design and formal verification of UAVs. In particular, the paper shows how our approach helps detecting early design errors. A UAV in charge of taking pictures serves as educational and running example throughout the paper. The SysML model of the UAV is simulated and formally verified using the free and open-source tool named TTool. This educational case study gives the authors of the paper an opportunity to draw lessons from teaching SysML.

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“…1) Developing architectures: The design process starts with capturing requirements and describing the dynamic behavior, for which models such as use case diagrams and sequence diagrams are used in MDSE [10]. Models aid in the requirements engineering process and, as a communication tool, contribute to efficient collaboration within developers [13]. The application architecture and design is planned before the actual implementation [14].…”

Section: A Use Cases Of Dynamic Interface Descriptionsmentioning

confidence: 99%

“…Such checks may detect incompatibilities already at design time. Early error detection can even facilitate development and reduce costs [13]. In some disciplines, verification is essential to fulfill strict safety requirements [14].…”

Section: )mentioning

confidence: 99%

Requirements for a dynamic interface model of IEC 61499 Function Blocks

Wiesmayr

Zoitl

2020

2020 25th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA)

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Component-based software engineering has emerged as a principle of software design to facilitate reuse and improve the software quality. This principle is supported by the domain-specific language IEC 61499, where Function Blocks are fully encapsulated software components. For a Function Block definition, a static interface description and an internal implementation are required. Service sequences describe the event flow at a component interface and are an optional dynamic interface model in IEC 61499. In general, dynamic interface models are a powerful tool for various use cases, yet service sequences are rarely used in practice due to their low expressiveness. Therefore, we identify the domain-specific requirements for a comprehensive dynamic interface model and use them for our analysis of service sequences, where several issues are identified.

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A feature-based classification of formal verification techniques for software models

Cited by 25 publications

References 108 publications

An efficient software verification using multi-layered software verification tool

An efficient software verification using multi-layered software verification tool

An Educational Case Study of Using SysML and TTool for Unmanned Aerial Vehicles Design

Requirements for a dynamic interface model of IEC 61499 Function Blocks

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