A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration

Vavousis, Alexandros; Apostolakis, A.; Psarakis, Mihalis

doi:10.1007/s10836-013-5420-x

Cited by 12 publications

(6 citation statements)

References 27 publications

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“…The techniques described in [14] and [19] employ PR to achieve fault tolerance of soft-core processors in FPGAs. As part of [15], the authors present a similar approach that does not require an external controller to handle the partial reconfiguration.…”

Section: Related Workmentioning

confidence: 99%

Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems

Dörr

Sandmann

Schade

et al. 2019

Lecture Notes in Computer Science

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Processor-based digital systems are increasingly being used in safety-critical environments. To meet the associated safety requirements, these systems are usually characterized by a certain degree of redundancy. This paper proposes a concept to introduce a redundant processor on demand by using the partial reconfiguration capability of modern FPGAs. We describe a possible implementation of this concept and evaluate it experimentally. The evaluation focuses on the fault handling latency and the resource utilization of the design. It shows that an implementation with 32 KiB of local processor memory handles faults within 0.82 ms and, when no fault is present, consumes less than 46 % of the resources that a comparable static design occupies.

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Section: Related Workmentioning

confidence: 99%

Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems

Dörr

Sandmann

Schade

et al. 2019

Lecture Notes in Computer Science

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“…For example, in MER, the existence of an error can be identified by reading voter status via the configuration port [12], [13]. After an error is detected, MER approaches typically recover the error by partially reconfiguring the erroneous module [14], [15]. In simple blind scrubbing, the RC refreshes the FPGA device by continuously rewriting the configuration memory [3].…”

Section: Related Workmentioning

confidence: 99%

A Programmable Configuration Controller for fault-tolerant applications

Gong

Nguyen

et al. 2016

2016 International Conference on Field-Programmable Technology (FPT)

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Abstract-FPGAs are promising candidates for computational tasks in space applications. However, they are susceptible to radiation-induced errors, the most common failure being due to the corruption of their configuration memory. Module-based partial reconfiguration and frame-based scrubbing are the two most commonly used techniques for detecting and recovering from configuration memory errors. Both methods require userdesigned reconfiguration controllers (RC) to read and write FPGA configuration memory data. This paper proposes a Programmable Configuration Controller (PCC) specifically designed for fault-tolerant applications. PCC has a soft Application Specific Instruction Set Processor (ASIP) architecture. The PCC is software programmable using the C language, which allows it to be used in a wide variety of fault-tolerant applications with minimal design and/or hardware overhead. PCC also has instruction extensions to accelerate commonly-used reconfiguration operations such as reading and writing configuration data. Through 5 case studies, we demonstrate that the use of an ASIP architecture for reconfiguration control in applications prone to radiation-induced corruption strikes the right balance between speed, resource utilization and flexibility.

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“…While the PE design we have considered in the DCT core consumes fewer resources than the capacity of a PRR, we choose the same as the minimum PRR size constrained by the vendor's tool and FPGA device under consideration. To reduce the memory size required in order to store configuration bistreams, a compression technique significantly reducing the storage space requirements of alternative partial bitstreams is presented in [52] and can be employed in future work. While partial reconfiguration is not a requirement for the DRFI scheme and the scheme is applicable to static designs as well, Partial Reconfiguration helps apportion large designs into independent testing domains.…”

Section: Comparisons and Tradeoffsmentioning

confidence: 99%

Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input

Imran

DeMara

2014

International Journal of Reconfigurable Computing

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Distance-Ranked Fault Identification (DRFI)is a dynamic reconfiguration technique which employs runtime inputs to conduct online functional testing of fielded FPGA logic and interconnect resources without test vectors. At design time, a diverse set of functionally identical bitstream configurations are created which utilize alternate hardware resources in the FPGA fabric. An ordering is imposed on the configuration pool as updated by the PageRank indexing precedence. The configurations which utilize permanently damaged resources and hence manifest discrepant outputs, receive lower rank are thus less preferred for instantiation on the FPGA. Results indicate accurate identification of fault-free configurations in a pool of pregenerated bitstreams with a low number of reconfigurations and input evaluations. For MCNC benchmark circuits, the observed reduction in input evaluations is up to 75% when comparing the DRFI technique to unguided evaluation. The DRFI diagnosis method is seen to isolate all 14 healthy configurations from a pool of 100 pregenerated configurations, and thereby offering a 100% isolation accuracy provided the fault-free configurations exist in the design pool. When a complete recovery is not feasible, graceful degradation may be realized which is demonstrated by the PSNR improvement of images processed in a video encoder case study.

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A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration

Cited by 12 publications

References 27 publications

Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems

Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems

A Programmable Configuration Controller for fault-tolerant applications

Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input

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