Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems

Abstract

Processor-based digital systems are increasingly being used in safety-critical environments. To meet the associated safety requirements, these systems are usually characterized by a certain degree of redundancy. This paper proposes a concept to introduce a redundant processor on demand by using the partial reconfiguration capability of modern FPGAs. We describe a possible implementation of this concept and evaluate it experimentally. The evaluation focuses on the fault handling latency and the resource utilization of the design. It shows that an implementation with 32 KiB of local processor memory handles faults within 0.82 ms and, when no fault is present, consumes less than 46 % of the resources that a comparable static design occupies.

Isolation Design Flow Effectiveness Evaluation Methodology for Zynq SoCs

“…Moreover, [21,22] also requires modification in DUT, such as insertion of Data Generator, Fault Generator, Error-detection, JTAG BSCAN modules and usage of external PCB hardware in order to emulate successful SEUs. Tobias et al in [23] proposed usage of Soft-core processor in combination with ICAP, to inject and mitigate faults within 0.82 ms of its generation at the overhead of 32 KiB MicroBlaze memory. However, using a soft-core processor not only incurs a toll on PL resources (routing and logic) but may lead to other side-effects suggested by Villalta et al in [5,24].…”

“…In the following, a methodology that significantly accelerates fault injection is presented and evaluated on a single chip cryptographic application i.e., AES core mapped onto a ZynQ SoC.Proposed methodology uses PCAP for non-intrusive FI, saving precious PL resources and additional PCB hardware or OCD tool [25] in comparison to existing methodologies in [21][22][23].…”

An Approach to Cost-Efficient Fault Tolerance in Inherently Redundant Fail-Operational Systems

“…The approach described in [3] is similar to those presented in [11] and [13] in the sense that a failure of a complex processor is handled by migrating its safety-critical functionality to a fallback processor. To reduce the resource consumption of the overall system, however, this fallback processor is not present in the fault-free case but introduced on demand by partially reconfiguring a field-programmable gate array (FPGA).…”

“…Fail-operational behavior refers to the property that even if a considered system is affected by errors, it remains able to deliver a certain minimum level of functionality [2], [3]. We refer to a system that is free of catastrophic consequences on users or the environment as safe [4] and define a fail-operational system as a system that can be safe only if it exhibits fail-operational behavior.…”