A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

A New architecture of Built-In Self-Diagnosis is presented in this project. The logic Built-In-Self-Test architecture method is extreme response compaction architecture. This architecture first time enables an autonomous on-chip evaluation of test responses with negligible hardware overhead. Architecture advantage is all data, which is relevant for a subsequent diagnosis, is gathered during just one test session. Due to some reasons, the existing method Built-In Self-Test is less often applied to random logic than to embedded memories. The generation of deterministic test patterns can become prohibitively high due to hardware overhead. The diagnostic resolution of compacted test responses is in many cases poor and the overhead required for an acceptable resolution may become too high. Modifications in Linear Feedback Shift Register to generate test pattern with security for modified Built-In-Self-Test applications with reduced power requirement. The modified Built-In-Self-Test circuit incorporates a fault syndrome compression scheme and improves the circuit speed with reduction of time.

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A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

Abstract: Abstract:In this paper, we propose a simulation-before-test (SBT)

Cited by 2 publications

References 8 publications

A design for testability approach for nano-CMOS analogue integrated circuits

A design for testability approach for nano-CMOS analogue integrated circuits

An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator

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