A design for testability approach for nano-CMOS analogue integrated circuits

Karmani, Mouna; Khedhiri, Chiraz; Hamdi, Belgacem; Man, Ka Lok; Tourki, Rached

doi:10.1080/00207217.2012.720957

Cited by 3 publications

(1 citation statement)

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“…The process of designing for a better testability is called design for testability (DFT). The DFT enables the designer to insert a test mechanism into each block of the embedded system design [3]. However, by inserting additional blocks in the embedded system design, the DFT mechanisms enable the access and management of the manipulated secret information in security‐critical systems.…”

Section: Introductionmentioning

confidence: 99%

The DFA/DFT‐based hacking techniques and countermeasures: Case study of the 32‐bit AES encryption crypto‐core

Karmani

Benhadjyoussef

Hamdi

et al. 2021

IET Computers & Digital Tech

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Integrated circuits (ICs) design plays a significant role in the embedded‐system performance, reliability and security. Thus, the constant advances in very large‐scale integration technology have led to design and manufacture of very complex ICs based on the System on a Chip (SoC) approach design. Therefore, the embedded system testing is considered earlier during the design process and testability is used as one of the objectives for evaluating safety‐critical embedded system designs. On the other hand, embedded systems used in critical applications execute security‐critical commands and collect sensitive data protected by cryptographic keys and authentication codes. The data and the unauthorised access of these embedded devices is an obvious target for attackers in order to obtain control or extract internal data. In this paper we consider that by using Design for Testability (DFT) approaches an attacker can control and affect a security‐critical embedded system. Thus, the authors focus on the DFT approach, as a means of violation of the security and confidentiality of embedded systems with security‐critical goals. In addition, with or without insertion of DFT circuitry, the crypto‐core is always exposed to the powerful differential fault analysis (DFA) attack. Here, a 32‐bit AES crypto‐core is used as a case study in order to analyse the DFA‐ and the DFT‐based Hacking techniques. A countermeasure was performed in order to avoid any scan or even DFA attack attempt.

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Section: Introductionmentioning

confidence: 99%