A fault coverage-driven partial scan chain selection technique

Abstract

Scan based design is a very popular approach to sequential circuit testing. Full scan designs often involve significant hardware and performance overheads. Partial scan design, with it's low overhead, offers an alternative to the f i l l scan design. The main problem in partial scan design is minimizing the magnitude of the set of flip-flops to be included in the scan chain. In the past, many solutions to this problem have been proposed. In this paper, we propose a fault coverage driven solution to this problem. Unlike ezisting techniques, our solution is targeted towards achieving 100% fault coverage while minimizing the set of flipflops to be included in the scan chain.