A dynamic element matching approach to ADC testing

Olleta, B.; Chen, Degang; Geiger, R.L.

doi:10.1109/mwscas.2002.1186920

Cited by 9 publications

(7 citation statements)

References 3 publications

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“…In [13]- [16], the authors propose dynamic element matching and deterministic dynamic element matching test algorithms that allow histogram testing of higher resolution ADCs using lower resolution/imprecise DACs. These methods reduce or eliminate the nonlinearity of the DAC outputs before using them to test the ADC.…”

Section: Prior Workmentioning

confidence: 99%

“…The key issue with the above test techniques is that they cannot be directly applied to test high resolution ADCs (20-24 bits) due to the large numbers of code measurements involved despite the research of [13]- [18] which indicates that the use of lower resolution and imprecise DACs to generate test stimulus for higher precision ADCs can be compensated in the back end by using intelligent signal and test data analysis techniques and algorithms. In addition, we desire a test methodology in which the complexity of the test procedure can be tuned to be commensurate with the degree of nonlinearity of a high-precision ADC as opposed to its bit precision.…”

Section: Prior Workmentioning

confidence: 99%

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Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Kook

Choi

Chatterjee

2013

IEEE Trans. VLSI Syst.

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A low-cost linearity test methodology for high-resolution analog-to-digital converters (ADCs) is presented in this paper. Linearity testing of ADCs requires high-precision digital-to-analog conversion (DAC) capability, commonly 3-bit higher resolution than the ADC under test. Further, a large number of ADC output data samples must be collected making conventional histogram testing impractical for high-resolution ADCs with 18-24 bit precision. In the proposed test methodology, two low-precision and low-cost DACs are used to generate a high-resolution ADC test stimulus. Significant reductions in test cost and test time are achieved by using low-cost instrumentation and by making fewer measurements than required for conventional histogram test. A least-squares-based polynomial fitting approach is used to determine the transfer function of the ADC under test. The generated transfer function is used to compute the non-linearity of the ADC accurately. No assumption is made regarding the linearity of the lower precision signal generators (DACs) used in the testing procedure. Software simulations and hardware experiments are performed to validate the proposed test methodology.Index Terms-Analog-to-digital converters (ADCs), automated test equipment (ATE), built-in-self-test (BIST), device under test (DUT), differential nonlinearity, digital-to-analog converters (DACs), integral nonlinearity.

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Section: Prior Workmentioning

confidence: 99%

Section: Prior Workmentioning

confidence: 99%

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Kook

Choi

Chatterjee

2013

IEEE Trans. VLSI Syst.

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“…The pattern used attempts to distribute the sources to be switched on in a way that all sources are used almost uniformly. As explained in [11] and [12], p represents the number of samples to be generated for each DAC input word.…”

Section: Ddem Methods For Thermometer Coded Dacsmentioning

confidence: 99%

“…This approach allows the signal generator to be realized with a not-soaccurate DAC, hence eliminating the need of large silicon area and reducing the cost of the test signal generator. In a preliminary study, a test strategy was introduced to use random DEM in a highly-nonlinear DAC to test low-resolution ADCs [11]. A new DDEM testing technique was also introduced and compared with the random DEM testing approach when a low accuracy DAC is used to characterize/test an ADC with higher linearity in [12].…”

Section: Introductionmentioning

confidence: 99%

Testing high resolution ADCs using deterministic dynamic element matching

Olleta

Jiang

Chen

et al.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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Dynamic element matching (DEM) is an effective approach to achieving good average performance in the presence of major mismatch in matching-critical circuits. This paper presents a deterministic DEM (DDEM) strategy for ADC testing that offers substantial reductions in testing cost.The approach is mathematically formulated and validated with simulation results that show the number of test vectors needed is comparable to what are currently used with standard code density linearity testing. It is demonstrated that the DDEM method can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique offers potential for use in both production test and BIST environments where high linearity devices are difficult to test and characterize.

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“…A preliminary study investigated the use of random DEM with a highly-nonlinear DAC to test low-resolution ADCs [10]. The idea behind DEM testing is to generate more than one DAC output samples as the ADC testing stimulus with a given DAC input digital word; each sample picks different elements following the DEM philosophy.…”

Section: Introductionmentioning

confidence: 99%

A Segmented Thermometer Coded DAC with Deterministic Dynamic Element Matching for High Resolution ADC Test

Jiang

Olleta

Chen

et al.

2005 IEEE International Symposium on Circuits and Systems

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ABSTRACT-Dynamic element matching (DEM) is an effective way to achieve good average performance in the presence of device mismatch, yet it has not been widely adopted because of the time-local stationarity of the signal path. This paper presents a DEM approach to ADC testing in which low precision DEM DACs are used to generate stimulus signals for the ADCs under test. A deterministic DEM (DDEM) switching scheme is applied to a segmented thermometer coded DAC architecture. Detailed simulation results are presented to verify the expected performance of the proposed testing approach. The new approach is able to accurately test ADCs with linearity that exceeds that of the original DAC used as the signal generator.The new architecture is suitable for production test and built-in-self-test (BIST) environments where high linearity ADCs are difficult to test and characterize.

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A dynamic element matching approach to ADC testing

Cited by 9 publications

References 3 publications

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Testing high resolution ADCs using deterministic dynamic element matching

A Segmented Thermometer Coded DAC with Deterministic Dynamic Element Matching for High Resolution ADC Test

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