A durable and energy efficient main memory using phase change memory technology

Zhou, Ping; Zhao, Bo; Yang, Jun; Zhang, Youtao

doi:10.1145/1555754.1555759

Cited by 709 publications

(378 citation statements)

References 19 publications

Supporting

Mentioning

378

Contrasting

Order By: Relevance

“…The phase change in GST can be achieved by heating a region of phase change material to a high temperature threshold using electrical-pulse generated Joule heat [5]. As shown in Fig.…”

Section: Phase Change Memory (Pcm)mentioning

confidence: 99%

See 1 more Smart Citation

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

Wang

Guan

et al. 2015

Computing

View full text Add to dashboard Cite

In embedded systems, especially battery-driven mobile devices, energy is one of the most critical performance metrics. Due to its high density and low standby power, phase change memory (PCM), an emerging non-volatile memory device, is becoming a promising dynamic random access memory (DRAM) alternative. Recent studies have proposed the hybrid main memory architecture integrating both PCM and DRAM to fully take advantage of the properties of both memories. However, the low power performance of PCM in the hybrid main memory architecture has not been fully explored. Therefore, it becomes an interesting problem to utilize PCM and DRAM as hybrid main memory for energy optimization in embedded systems. In this paper, we present an energy optimization technique for hybrid main memory architecture. The objective is to fully utilize PCM to reduce the energy consumption while ensuring that the real-time performance of applications are guaranteed. We propose a two-phase approach to solve hybrid main memory address mapping problem. In the first phase, we calculate energy and time cost for each address based on the task models. Then the applications can be modeled as data-flow graph nodes, and different access times will associate with different energy consumption. In the second phase, for different memory types and the given timing constraint, we formulate the scheduling problem as an integer linear programming (ILP) model and obtain an optimal solution. The 123 G. Wang et al.ILP model can map a proper memory type for each address such that the total energy consumption can be minimized while the timing constraint is satisfied. In addition, we propose a heuristic approach to efficiently obtain a near-optimal solution. We conduct experiments on an ARM-based simulator. The experimental results show that our method can effectively reduce the energy consumption with the least system cost compared with the previous work.

show abstract

“…The phase change in GST can be achieved by heating a region of phase change material to a high temperature threshold using electrical-pulse generated Joule heat [5]. As shown in Fig.…”

Section: Phase Change Memory (Pcm)mentioning

confidence: 99%

“…Several techniques have been proposed to reduce write activities of PCM including differential write [5], compression [11,12], Flip-N-Write [13], and row-buffer locality-aware data placement [14]. Zhou et al [5] proposed a set of techniques, such as redundant bit removal and row shifting, to prolong the lifetime of PCMbased main memory.…”

Section: Related Workmentioning

confidence: 99%

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

Wang

Guan

et al. 2015

Computing

View full text Add to dashboard Cite

show abstract

“…Their design results in up to 3× speedup. Another study by Zhou et al [65] tackled the same problem with a different architecture design. They proposed a 3D die stacked chip multiprocessor design which deploys processors and the main memory in the same chip.…”

Section: Main Memory Design With Nvmsmentioning

confidence: 99%

Memory and Storage System Design with Nonvolatile Memory Technologies

Zhao

Chi

et al. 2015

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

Abstract:The memory and storage system, including processor caches, main memory, and storage, is an important component of various computer systems. The memory hierarchy is becoming a fundamental performance and energy bottleneck, due to the widening gap between the increasing bandwidth and energy demands of modern applications and the limited performance and energy efficiency provided by traditional memory technologies. As a result, computer architects are facing significant challenges in developing high-performance, energy-efficient, and reliable memory hierarchies. New byte-addressable nonvolatile memories (NVMs) are emerging with unique properties that are likely to open doors to novel memory hierarchy designs to tackle the challenges. However, substantial advancements in redesigning the existing memory and storage organizations are needed to realize their full potential. This article reviews recent innovations in rearchitecting the memory and storage system with NVMs, producing high-performance, energy-efficient, and scalable computer designs.

show abstract

“…In large systems, a memory system is one of the major sources of energy consumption. Using non-volatile random access memory (NVRAM) in the memory system creates much attention recently because NVRAMs consume zero leakage power in memory cells [1]. Phase change memory (PCM) is one of the most promising technologies for the NVRAM based memory system.…”

Section: Introductionmentioning

confidence: 99%

“…Phase change memory (PCM) is one of the most promising technologies for the NVRAM based memory system. However, PCM has write latencies roughly 6-10 times slower than that of DRAM [1,2]. Moreover, its lifetime is much shorter than DRAM due to the limited number of write operations allowed to each PCM cell [3].…”

Section: Introductionmentioning

confidence: 99%

An optimal DRAM sizing and partitioning method for NVRAM based hybrid memory architecture

Lim

Song

Lee

2014

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:We propose an optimal method for sizing and partitioning DRAM in the NVRAM based hybrid memory for a multicore system. Optimizing the size of DRAM in the hybrid memory is critical to capture the working sets of applications for performance improvement and reduce hardware cost. Given the QoS requirements of applications and architectural constraints, the proposed method can minimize the total DRAM size by determining optimal partitions using integer linear programming. It can be used to statically size the DRAM during a system design phase or dynamically partition the DRAM among applications under various runtime scenarios.

show abstract

A durable and energy efficient main memory using phase change memory technology

Cited by 709 publications

References 19 publications

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

Memory and Storage System Design with Nonvolatile Memory Technologies

An optimal DRAM sizing and partitioning method for NVRAM based hybrid memory architecture

Contact Info

Product

Resources

About