A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process

Desai, Shaishav; Trivedi, P.; Kanael, V. Von

doi:10.1109/isscc.2007.373417

Cited by 6 publications

(5 citation statements)

References 6 publications

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“…where the first term represents the desired VCO output voltage oscillating at , while the second term is the interference due to the aggressor VCO as expressed by (3). Using the phasor representation in Figure 4 and assuming that , ≪ , the victim's output voltage may be rewritten as…”

Section: Clock Jitter In Plesiochronous Neighboring Pllsmentioning

confidence: 99%

“…The design of clock multipliers for multirate multistandard applications involves a tradeoff between the output clock jitter and the frequency tuning range. Traditionally, a wide range is achieved via non-LC-based oscillators such as relaxation or ring oscillators [1][2][3] at the cost of higher phase noise and intrinsic jitter. LC VCOs are used for lowjitter multigigahertz applications, but their tuning range is inherently small [2,4].…”

Section: Introductionmentioning

confidence: 99%

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Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

Molavi

Djahanshahi²,

Zavari³

et al. 2013

Journal of Electrical and Computer Engineering

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Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance. This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner. Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to 5.8 GHz is designed and implemented in a 65 nm digital CMOS process. Measurement results are presented for densely integrated CSUs within a multirate multiprotocol system-on-chip PHY device.

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Section: Clock Jitter In Plesiochronous Neighboring Pllsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

Molavi

Djahanshahi²,

Zavari³

et al. 2013

Journal of Electrical and Computer Engineering

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“…As the design progresses towards the physical implementation stage, power is re-estimated with actual parasitic extraction using commercial tools. Good correlation was found between the in-house RTL-level tool and the transistor-level simulation accounting for parasitics, as shown in Two PLLs provide the variable frequencies for the core and fixed frequencies for the I/O and memory subsystem [2]. Debugging functions such as stretch/squeeze/stop of clocks are built into the balanced H-tree clock distribution.…”

mentioning

confidence: 93%

“…Two PLLs provide the variable frequencies for the core and fixed frequencies for the I/O and memory subsystem [2]. Debugging functions such as stretch/squeeze/stop of clocks are built into the balanced H-tree clock distribution.…”

mentioning

confidence: 99%

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems

Chen¹,

Ananthanarayanan²,

Biswas³

et al. 2007

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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The PA6T-1682M SoC targets applications including compute servers, networking, imaging and storage applications [1]. It integrates two 2GHz Power TM architecture cores, a shared 2MB L2, a coherent crossbar interconnect, two 1066MHz DDR2 64b memory channels, a configurable I/O subsystem able to support two 10Gb and four 1Gb Ethernet MAC, eight PCI Express links of configurable width with an aggregate bandwidth of 6GB/s, and hardware acceleration for cryptography, XOR and network functionalities. The functional block diagram is shown in Fig. 5.5.1. The chip die size is 115mm 2 , implemented in a 65nm triple-V t , dual-oxide 8M CMOS process.The maximum thermal design power is 25W. To achieve this efficiency, the cores have power-saving modes in addition to various active modes, as shown in Fig. 5.5.2. Each core has an independent supply (V DDcpu ), which can be shut down when there is no active workload. This arrangement also enables each core to operate with its own minimum required V DD under the presence of inter-core process and temperature variation. The SRAM arrays have their own V DD supply. The writability of the SRAM cell would otherwise be the limiting factor for the minimum core V DD . The memory and I/O subsystem has its own V DD , which is lower than the technology maximum for additional power savings.Low-voltage operation exacerbates the impact of PVT variations, so the design flow is enhanced to deal with such variations. Monte Carlo simulations are used to characterize critical circuit elements to optimize device sizing. Post processing of the static timing results compensates for the impact of statistical variations on the margin. Low-V t cell swapping into critical paths shapes timing histograms and improves speed yield. In this scheme, noncritical devices with a safe design margin are swapped with a longer channel version to reduce leakage power. Longer channel devices are chosen instead of high V t transistors because of their better voltage scalability and better trade-off of performance versus standby current.Clock gating is extensively used (23,000 instances) as an intrinsic way to implement logic functions and to save power. In-house tools gather flip-flop toggling statistics at the RTL stage of the design and provide early feedback on the effectiveness of clock gating in each functional unit. As the design progresses towards the physical implementation stage, power is re-estimated with actual parasitic extraction using commercial tools. Good correlation was found between the in-house RTL-level tool and the transistor-level simulation accounting for parasitics, as shown in Fig. 5.5.3.Two PLLs provide the variable frequencies for the core and fixed frequencies for the I/O and memory subsystem [2]. Debugging functions such as stretch/squeeze/stop of clocks are built into the balanced H-tree clock distribution. The changing core V DD poses challenges for the clocking scheme. The coherent crossbar and functional units it connects to, such as the L2, are clocked at half the core frequency. Due to ...

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“…Various methods of making clock multipliers directly on-chips have been presented in the open literature. These conventional approaches use phase locked loops (PLLs) or delay-locked loops (DLLs), [1][2][3], which have the advantage of correcting the clock phase error in the circuit by itself. PLLbased clock multipliers, however, are known to suffer from frequency drifting and electromagnetic interference (EMI) problems.…”

Section: Introductionmentioning

confidence: 99%

On-chip sine wave frequency multiplier for 40-GHz signal generator

Surano

Bonizzoni

Maloberti

2009

2009 Ph.D. Research in Microelectronics and Electronics

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This paper presents a novel signal frequency multiplier for very high speed applications. The proposed circuit is based on a simple but effective folding cell and it is able to generate an output at four times the frequency of the differential sine wave input. The circuit has been designed and optimized for a 40-nm CMOS technology and it has been fully simulated at the transistor level. Possible fabrication and timing mismatches are corrected with foreground calibration. Simulation results shows that the multiplier can provide an output signal at 40 GHz starting from a 10-GHz input signal consuming about 5 mW.

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A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process

Cited by 6 publications

References 6 publications

Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems

On-chip sine wave frequency multiplier for 40-GHz signal generator

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