Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

Abstract

Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance. This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner. Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to 5.8 GHz is designed and implemented in a 65 nm digital CMOS process. Measurement results are presented for densely integrated CSUs within a multirate multiprotocol system-on-chip PHY device.

A generation and distribution system of clock signal source for signal acquisition system

“…The single‐PLL clock chips working beyond 1 GHz has the clock jitter accuracy that is usually several hundred femtoseconds. For example, Molavi et al proposed a clock chip working in the frequency range of 3.6–5.8 GHz and the clock jitter accuracy of which is ˜500 fs 16 . Bonfanti et al developed a clock chip working in the frequency of 2.29–2.75 GHz and the jitter is ˜970 fs at 2.75 GHz 17 .…”

“…For example, Molavi et al proposed a clock chip working in the frequency range of 3.6-5.8 GHz and the clock jitter accuracy of which is ∼500 fs. 16 Bonfanti et al developed a clock chip working in the frequency of 2.29-2.75 GHz and the jitter is ∼970 fs at 2.75 GHz. 17 We should note that a single PLL clock generator will amplify the clock jitter and introduce its own jitter.…”