2010
DOI: 10.1016/j.mejo.2009.11.005
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A dual mode UHF EPC Gen 2 RFID tag in 0.18 μm CMOS

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Cited by 9 publications
(5 citation statements)
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“…For this design, the power consumption is equal to 0.47mW. This is relative high as compare to [5], but the latter employed very complex power optimization techniques such as clock gating and operand isolation to achieve 0.22 mW.…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…For this design, the power consumption is equal to 0.47mW. This is relative high as compare to [5], but the latter employed very complex power optimization techniques such as clock gating and operand isolation to achieve 0.22 mW.…”
Section: Discussionmentioning
confidence: 99%
“…The wake up mode is designed to be power sensitive, where it will be waked-up only when it is located in the interrogating field. Najafi et al [5] used elaborated clock gating and operand isolation techniques.…”
Section: Introductionmentioning
confidence: 99%
“…In the physical layer, the forward link is achieved by ASK modulation using Pulse-Interval Encoding (PIE) while in the backward link, the tags broadcast its ID to the interrogator by backscattering the amplitude and/or phase of the Radio Frequency carrier modulation by means of FM0 or Miller-Modulated Subcarrier (MMSC) encoding scheme. The protocol can include several data rate ranges, i.e., [26.7-128 kbps] for the forward link and [5-640 kbps] for the backward link [18]. Also, the communication link is halfduplex.…”
Section: Epc Gen2 Principalmentioning
confidence: 99%
“…The number of clock cycles during the RTCal signal is calculated and then divided by two to fix a pivot threshold. If the number of cycles is less than this threshold, the signal is a data-0 symbol, else, it is a data-1 symbol [18]. In the tag Identification Layer, the reader accomplishes the tag population by three elementary operations.…”
Section: Epc Gen2 Principalmentioning
confidence: 99%
“…In [2] the signal envelope is consistently compared with the fixed voltage which causes difficulty in the data detection in low voltages of RF input signal. The LPF stage in [3, 4] includes RC circuit which has the drawback of large resistor and capacitor for decreasing the rapid variation of envelope voltage. The RC circuit in [5] consists of weighted resistors which culminate in high chip area.…”
Section: Introductionmentioning
confidence: 99%