2017 International Conference on System Science and Engineering (ICSSE) 2017
DOI: 10.1109/icsse.2017.8030977
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A dual-mode 1.8 V-output DC-DC buck converter with on-chip capacitor multiplier in 0.18 um CMOS

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Cited by 1 publication
(2 citation statements)
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“…This condition usually leads to a large value for C1, rendering it difficult and/or expensive to integrate [7]. Another design challenge is to maintain the pole and zero defined by (5) in suitable locations, despite inevitable PVT variations.…”
Section: B Gm-rc Frequency Compensation Network Based On the Proposed...mentioning
confidence: 99%
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“…This condition usually leads to a large value for C1, rendering it difficult and/or expensive to integrate [7]. Another design challenge is to maintain the pole and zero defined by (5) in suitable locations, despite inevitable PVT variations.…”
Section: B Gm-rc Frequency Compensation Network Based On the Proposed...mentioning
confidence: 99%
“…An effective way to reduce the die area occupied by the integrated compensation network is to implement the large capacitor required by using a capacitor multiplier. For example, the AO-RC Type-II compensation network presented in [5] is implemented by a floating capacitor multiplier. Reference [6] reports a buck converter with fully integrated compensation network based on a capacitor multiplier; the Gm-RC compensation network implemented by a capacitor multiplier resulted in a fast transient response of the convertor presented in [7].…”
Section: Introductionmentioning
confidence: 99%