A Dual-Gate Graphene FET Model for Circuit Simulation—SPICE Implementation

Umoh, Ime J.; Kázmierski, Tom J.; Al-Hashimi, Bashir M.

doi:10.1109/tnano.2013.2253490

Cited by 29 publications

(31 citation statements)

References 37 publications

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“…The electron contribution towards the drain current is determined by saturation displacement current (Idisp) as proposed by Umoh et. al [13] where is the alterative carrier mobility:…”

Section: B Drain Current Modelmentioning

confidence: 99%

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Bending effects in a flexible dual gated graphene FET: A Verilog-A model implementation

Yogeswaran

Tang

Vinciguerra

et al. 2017

2017 European Conference on Circuit Theory and Design (ECCTD)

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Abstract-This paper presents the Verilog-A implementation of charge control based model of dual gated graphene field effect transistor (GFET) and initial results towards bending induced changes in their electrical response. The ambipolar region of the device has been described using the saturation and displacement current models. The output characteristics derived from Verilog -A simulation is in good agreement with the reported experimental results. The model has been extended to study the behaviour of a bendable GFET and the simulation indicates negligible change in the electrical properties in the test range of bending.

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“…The electron contribution towards the drain current is determined by saturation displacement current (Idisp) as proposed by Umoh et. al [13] where is the alterative carrier mobility:…”

Section: B Drain Current Modelmentioning

confidence: 99%

“…al [12] and Umoh et. al [13]. The proposed model has been implemented in Verilog-A, which is widely used for circuit modelling [14,15].…”

Section: Introductionmentioning

confidence: 99%

Bending effects in a flexible dual gated graphene FET: A Verilog-A model implementation

Yogeswaran

Tang

Vinciguerra

et al. 2017

2017 European Conference on Circuit Theory and Design (ECCTD)

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“…Hence, by applying the Drude model, the quantum capacitance, C q , takes into consideration the capacitance due to both the minimum charge and the induced charge into the channel [22,23]. Thus, Eqs.…”

Section: Capacitance Modelmentioning

confidence: 99%

“…The I-V characteristic of bilayer graphene has been reported to have three regions [21,22]. For field effect transistors the gate capacitance modulates the source potential barrier.…”

Section: Carrier Transportmentioning

confidence: 99%

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A circuit model for defective bilayer graphene transistors

Umoh

Moktadir

Hang

et al. 2016

Solid-State Electronics

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a b s t r a c tThis paper investigates the behaviour of a defective single-gate bilayer graphene transistor. Point defects were introduced into pristine graphene crystal structure using a tightly focused helium ion beam. The transfer characteristics of the exposed transistors were measured ex-situ for different defect concentrations. The channel peak resistance increased with increasing defect concentration whilst the on-off ratio showed a decreasing trend for both electrons and holes. To understand the electrical behaviour of the transistors, a circuit model for bilayer graphene is developed which shows a very good agreement when validated against experimental data. The model allowed parameter extraction of bilayer transistor and can be implemented in circuit level simulators.

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