A dual execution pipelined floating-point CMOS processor

Reduced latency IEEE floating-point standard adder architectures

“…A multiplexer at the output of the near and far data paths selects the correct result at the completion of the second pipeline stage. As noted in the introduction, some recent microprocessors have used this method to speed up FP addition [12], [5].…”

“…Floating-point (FP) addition is the most frequent FP operation and FP adders are therefore critically important components in modern microprocessors [4,6,7,12,5] and digital signal processors [23]. FP adders must be fast to match the increasing clock rates demanded by deep submicron technologies with a small number of pipelining stages to minimise latency and improve branch resolution time.…”

“…They also discuss how to construct faster FP adders. Implementations of FP adders are reported in [6,7,12,5,9,13,10]. Algorithms and circuits which have been used to improve their design are described in [17,8,3,20,16,21,15,22,19].…”

“…Other FP adder designs have moved the rounding stage before the normalisation [21,19,12]. Quach and Flynn describe an FP adder [21] which uses a compound significand adder with two outputs plus a row of half adders and effectively has a duplicated carry chain.…”

“…Quach and Flynn describe an FP adder [21] which uses a compound significand adder with two outputs plus a row of half adders and effectively has a duplicated carry chain. Kowaleski et al [12] describe an adder as part of a 263,000 transistor FP unit which contains separate add and multiply pipelines with a latency of 4-cycles at 433M H z in a 0:35m process. The significands are simultaneously added and rounded by employing a half adder which makes available a LSB for the case where a "1" is added for taking the two's complement of one input.…”