Reducing the mean latency of floating-point addition

Oberman, Stuart F.; Flynn, Michael J.

doi:10.1016/s0304-3975(97)00201-6

Cited by 7 publications

(4 citation statements)

References 12 publications

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“…The rounding position within the LSD corresponds to the leading 1 in the MSD, except that conversion to nonredundant format may shift the leading 1 to the right by one position. There would be no propagating 1 during the conversion process, given that the radix-16 digits of the converted result can accommodate the SUT digits in [0,8]. However, negative SUT digits in [À9, À1] generate a propagating À1, leaving behind a radix-16 digit in [7,15].…”

Section: Resultsmentioning

confidence: 99%

“…As another example, the stored-posibit-transfer (SPT) encoding [18] of the radix-16 digit set [À8, 8], where there can be at most one leading insignificant 1 (À1) followed to the right by À8 (8), obviates the need for any complex provision to convert leading insignificant nonzero digits. But the active hardware replication factor of the SPT adder is only modestly less than that in the design of Fahmy and Flynn.…”

Section: Redundant Representationsmentioning

confidence: 99%

“…Each of the steps above may consist of a number of simpler substeps. To minimize the addition latency, clever methods have been developed to allow concurrent execution of (sub)steps in Algorithm 1 (e.g., [6], [7], [8], [9]). Rounding, in particular, is problematic, because it could introduce a second power/area-intensive word-width addition (actually, an incrementation).…”

Section: Introductionmentioning

confidence: 99%

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Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

Jaberipur

Parhami

Gorgin

2010

IEEE Trans. Comput.

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Abstract-Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a new redundant-digit representation for floating-point numbers that leads to computation speedup in two ways: 1) Reducing the per-operation latency when multiple floating-point additions are performed before result conversion to nonredundant format and 2) Removing the addition associated with rounding. While the first of these advantages is offered by other redundant representations, the second one is unique to our approach, which replaces the power-and area-intensive rounding addition by low-latency insertion of a rounding two-valued digit, or twit, in a position normally assigned to a redundant twit within the redundant-digit format. Instead of conventional sign-magnitude representation, we use a sign-embedded encoding that leads to lower hardware redundancy, and thus, reduced power dissipation. While our intermediate redundant representations remain incompatible with the IEEE 754-2008 standard, many application-specific systems, such as those in DSP and graphics domains, can benefit from our designs. Description of our radix-16 redundant representation and its addition algorithm is followed by the architecture of a floating-point adder based on this representation. Detailed circuit designs are provided for many of the adder's critical subfunctions. Simulation and synthesis based on a 0:13 m CMOS standard process show a latency reduction of 15 percent or better, and both area and power savings of around 58 percent, compared with the best designs reported in the literature.

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Section: Resultsmentioning

confidence: 99%

Section: Redundant Representationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

Jaberipur

Parhami

Gorgin

2010

IEEE Trans. Comput.

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“…Various design techniques are proposed to improve the performance of FPA to increase its speed [24][25][26][27][28], to reduce its silicon area [29], dealing with denormalized numbers [30] and rounding logic [31] and implementing FPA using field programmable gate array (FPGA) [32,33]. A Leading Zero Anticipator (LZA) is also designed for normalization process in dual path algorithm to improve the speed of FPA [34][35][36][37][38], and extensive research articles are available for synchronous FPA [39][40][41][42][43][44][45].…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

2020

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Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently used for real number addition because floating-point representation provides a large dynamic range. Most of the existing FPA designs are synchronous and their activities are coordinated by clock signal(s). However, technology scaling has imposed several challenges like clock skew, clock distribution, etc., on synchronous design due to presence of clock signal(s). Asynchronous design is an alternate approach to eliminate these challenges imposed by the clock, as it replaces the global clock with handshaking signals and utilizes a communication protocol to indicate the completion of activities. Bundled data and dual-rail coding are the most common communication protocols used in asynchronous design. All existing asynchronous floating-point adder (AFPA) designs utilize dual-rail coding for completion detection, as it allows the circuit to acknowledge as soon as the computation is done; while bundled data and synchronous designs utilizing single-rail encoding will have to wait for the worst-case delay irrespective of the actual completion time. This paper reviews all the existing AFPA designs and examines the effects of the selected communication protocol on its performance. It also discusses the probable outcome of AFPA designed using protocols other than dual-rail coding.

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Floating-Point Representation, Algorithms, and Implementations

Ercegovac

2004

Digital Arithmetic

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Reducing the mean latency of floating-point addition

Cited by 7 publications

References 12 publications

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

Floating-Point Representation, Algorithms, and Implementations

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