A dual core oxide 8T SRAM cell with low Vccmin and dual voltage supplies in 45nm triple gate oxide and multi Vt CMOS for very high performance yet low leakage mobile SoC applications

Liu, Ping; Wang, Joseph; Phan, Michael; Garg, Manish; Ron, Zhang; Cassier, Amer; Chua-Eoan, Lew; Andreev, Boris D.; Weyland, Sebastien; Ekbote, S.; Han, Michael; Fischer, Jeff; Yeap, Geoffrey; Wang, Ping-Wei; Li, Quincy; Hou, Chin-Shan; Lee, S.B.; Wang, Y.F.; Lin, Shy-Jay; Cao, Min; Mii, Y. J.

doi:10.1109/vlsit.2010.5556200

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“…This becomes very clear at the design level by assessing the positive impact of FDSOI on the 6T SRAM. Standard bulk Si technology beyond the 28/32nm node faces the tradeoff between increasing the SRAM cell area by implementing the 8T or 10T SRAM cell to achieve high performance and low leakage or maintaining a 6T cell with high V DD (>1V) (11)(12).…”

Section: Fully Depleted Mosfetmentioning

confidence: 99%