A dual basis bit-serial systolic multiplier for GF(2 )

Fenn, S.T.J.; Taylor, David J.; Benaïssa, Mohammed

doi:10.1016/0167-9260(95)00007-3

Cited by 14 publications

(18 citation statements)

References 13 publications

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“…From the evaluated results obtained in Table 1, we observe that the developed multiplier structure has a significantly lower number of gates (2 m AND gates, 2 m XOR gates, zero MUXes, and 8 m D‐Latches) with extra m Tri‐State buffers compared to several multiplier structures. Only Fenn [6] multiplier has almost the same number of XOR gates (2 m − 1) as the developed multiplier. Also, we can observe that the latency of the non‐systolic multiplier structures [12,38] are significantly lower than the proposed one, but with a considerably higher CPD.…”

Section: Resultsmentioning

confidence: 99%

“…Also, we can observe that the latency of the non‐systolic multiplier structures [12,38] are significantly lower than the proposed one, but with a considerably higher CPD. Also, the multiplier of Fenn [6] has the same latency and slightly lower CPD compared to the suggested one. Therefore, it slightly outperforms the proposed design in terms of delay.…”

Section: Resultsmentioning

confidence: 99%

“…The results registered in Table 2 indicate that the suggested bit‐serial systolic array multiplier significantly outperforms the previously published competent bit‐serial multipliers in terms of area ( A ) and area‐time ( AT ) complexity by percentage values of at least 25.4% and 33.2%, respectively. By observing Table 2, we notice that the multiplier structures of [5,6,11,13,16] have a reasonable area and delay complexity compared to the other multiplier structures. Therefore, the developed multiplier structure and these multipliers are modelled using VHDL hardware description language for field size m = 233.…”

Section: Resultsmentioning

confidence: 99%

“…Multiplication over GF (2 m ) is at the heart of the computation methodology of these applications. Since this operation is very costly in terms of area and delay complexities, it is given considerable considerations in the literature to reduce its space and delay overhead [3][4][5][6][7][8][9][10][11][12][13][14][15][16].…”

Section: Introduction and Related Workmentioning

confidence: 99%

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Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 ^m )

Ibrahim

2021

IET Computers & Digital Tech

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This article offers a new bit‐serial systolic array architecture to implement the interleaved multiplication algorithm in the binary‐extended field. The exhibited multiplier structure is more proper for VLSI implementation as it has regular cell structures as well as local communication wires between the cells. The ASIC implementation results of the suggested bit‐serial multiplier structure and the existing competitive bit‐serial multiplier structures previously described in the literature indicate that the recommended design achieves a notable reduction in area and significant improvement of area‐time complexities by at least 28.4% and 35.7%, respectively. Therefore, it is more proper for cryptographic applications forcing more restrictions on the space.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 ^m )

Ibrahim

2021

IET Computers & Digital Tech

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“…The PEs perform a specific task and can be organized in one-dimensional or two-dimensional space. The systolic multiplier structures can be arranged in bit-parallel [4,5,8,[22][23][24][25][26][27] or bitserial systolic structures [2,28,29]. Bit-parallel systolic architectures are well known for their significant area cost and high power consumption.…”

Section: Literature Reviewmentioning

confidence: 99%

Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices

et al. 2022

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Security and privacy issues with IoT edge devices hinder the application of IoT technology in many applications. Applying cryptographic protocols to edge devices is the perfect solution to security issues. Implementing these protocols on edge devices represents a significant challenge due to their limited resources. Finite-field multiplication is the core operation for most cryptographic protocols, and its efficient implementation has a remarkable impact on their performance. This article offers an efficient low-area and low-power one-dimensional bit-parallel systolic implementation for field multiplication in GF(2n) based on an irreducible all-one polynomial (AOP). We represented the adopted multiplication algorithm in the bit-level form to be able to extract its dependency graph (DG). We choose to apply specific scheduling and projection vectors to the DG to extract the bit-parallel systolic multiplier structure. In contrast with most of the previously published parallel structures, the proposed one has an area complexity of the order O(n) compared to the area complexity of the order of O(n2) for most parallel multiplier structures. The complexity analysis of the proposed multiplier structure shows that it exhibits a meaningful reduction in area compared to most of the compared parallel multipliers. To confirm the results of the complexity analysis, we performed an ASIC implementation of the proposed and the existing efficient multiplier structures using an ASIC CMOS library. The obtained ASIC synthesis report shows that the proposed multiplier structure displays significant savings in terms of its area, power consumption, area-delay product (ADP), and power-delay product (PDP). It offers average savings in space of nearly 33.7%, average savings in power consumption of 39.3%, average savings in ADP of 24.8%, and savings in PDP of 31.2% compared to the competitive existing multiplier structures. The achieved results make the proposed multiplier structure more suitable for utilization in resource-constrained devices such as IoT edge devices, smart cards, and other compact embedded devices.

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VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases

Rahaman

Mathew

Jabir

et al. 2012

Progress in VLSI Design and Test

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A dual basis bit-serial systolic multiplier for GF(2 )

Cited by 14 publications

References 13 publications

Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 ^m )

Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 ^m )

Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases

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A dual basis bit-serial systolic multiplier for GF(2 )

Cited by 14 publications

References 13 publications

Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 m )

Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 m )

Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases

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Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 ^m )

Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 ^m )