A DSP-based turbo codec for 3G communication systems

Jiang, Yingtao; Tang, Yiyan; Wang, Yuke; Zhou, Dian

doi:10.1109/icassp.2002.5745201

Cited by 2 publications

(2 citation statements)

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“…We simulated the bit error rate of the implemented regular LDPC decoder using a codeword length of N = 10228 and compared the performance with a Turbo decoder using an 8-state component encoder and an even-odd interleaver described in [5] with the same block length. The Turbo code was punctured by transmitting the two parity sequences alternatively to achieve the same rate as the LDPC code.…”

Section: Simulation Resultsmentioning

confidence: 99%

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Efficient DSP implementation of an LDPC decoder

Lechner

Sayir

Rupp

2004 IEEE International Conference on Acoustics, Speech, and Signal Processing

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We present a high performance implementation of a belief propagation decoder for decoding low-density parity-check (LDPC) codes on a fixed point digital signal processor. A simplified decoding algorithm was used and a stopping criteria for the iterative decoder was implemented to reduce the average number of required iterations. This leads to an implementation with increased throughput compared to other implementations of LDPC codes or Turbo codes. This decoder is able to decode at 5.4Mbps on a Texas Instruments TMS320C64xx DSP running at 600MHz.

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Section: Simulation Resultsmentioning

confidence: 99%

“…For a DSP running at a clock frequency of 600MHz and an average number of 10 iterations, this results in a data throughput of 5.4Mbps. This implementation is approximately 2.6 times faster than a comparable Turbo Decoder implemented on the same type of DSP [5]. However, the Turbo decoder needs fewer iterations to converge.…”

Section: Implementation Requirementsmentioning

confidence: 96%