2008
DOI: 10.1109/tce.2008.4470037
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A DSP Based H.264 Decoder for a Multi-Format IP Set-Top Box

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Cited by 21 publications
(14 citation statements)
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“…The performance and power consumption (measured on Agilent 93 K platform) of the fabricated SoC for HD H.264 decoding (because this format is the most complex one) are compared with those of four state-of-the-art designs (Table I). The reference designs include a coarse-grained array processor [3], a industrial DSP processor [4], a many-core processor (with two 32-core clusters) [5] and a dedicated hardwired multi-format video codec [9] (ASIC design). All these processors are domain-specific architectures developed to accelerate multi-format video encoding/decoding.…”
Section: Implementation Results and Comparisonsmentioning
confidence: 99%
See 1 more Smart Citation
“…The performance and power consumption (measured on Agilent 93 K platform) of the fabricated SoC for HD H.264 decoding (because this format is the most complex one) are compared with those of four state-of-the-art designs (Table I). The reference designs include a coarse-grained array processor [3], a industrial DSP processor [4], a many-core processor (with two 32-core clusters) [5] and a dedicated hardwired multi-format video codec [9] (ASIC design). All these processors are domain-specific architectures developed to accelerate multi-format video encoding/decoding.…”
Section: Implementation Results and Comparisonsmentioning
confidence: 99%
“…1). Previous studies [3,4,5] have demonstrated that these tasks are mostly block-based word-level calculations that can potentially be processed in parallel. The design challenge lies in selecting the optimal hardware architecture that could efficiently exploit such parallelism.…”
Section: Introductionmentioning
confidence: 99%
“…The methodologies presented in [16] [17] are been applied to reduce the time spent to decode the H.264/SVC sequences. These methodologies improve the decoder performance taking advantage of the SIMD (Simple Instruction Multiple Data) architecture, using explicit DMA transfers to move data between internal and external memory and allocating code and data in the different levels of internal memory to reduce the cache misses (the first results obtained after the optimization process can be checked at [18]).…”
Section: B) Performance Resultsmentioning
confidence: 99%
“…Now our previous experience [13] [26] is currently been applied to the optimization of this decoder. Extrapolating the results we have obtained for other decoders, real-time operation for SD pictures can be forecasted.…”
Section: Discussionmentioning
confidence: 99%
“…In our previous work [11] [12] [13], MPEG-2, MPEG-4 and H.264 decoders have been ported and optimized for different DSPs and a methodology to implement real-time video decoders has been extracted from this previous experience [13].…”
Section: Introductionmentioning
confidence: 99%