A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM

Abstract

A double sensing with selective bitline voltage regulation (DS-SBVR) scheme is proposed to improve the throughput of ultralow-voltage static random access memory (SRAM). It senses the bitline voltage swing twice and compares two samples for confirmation. The bitline voltage is dynamically regulated by charge sharing between two sensing steps. Different from other timing speculative SRAMs, its error flag is generated much earlier; therefore, it achieves a higher reading throughput. Meanwhile, a digitized timing scheme is proposed to generate configurable timing pulses for the DS-SBVR. Compared with other timing techniques, it has a better ability to process, voltage, temperature (PVT) tracking and variance suppression. For fair comparison of performance/power/area, three different columnbased timing speculative designs are implemented in the same technology. A 28-nm test chip including 40 SRAM macros (128 × 32) is fabricated to demonstrate the scheme. Compared with the conventional design, measurements show that DS-SBVR achieves 1.45× throughput gain at 0.6-V SS corner. The figure of merit (FOM) is introduced for power, performance, and area (PPA) gain comparison. Compared with the conventional design, the FOMs of PPA gain are 1.54 and 2.33 in 128-row and 512-row memories, respectively. Compared with other timing speculative SRAMs, it achieves 1.83×-2.24× improvement.

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

“…For example, a complex roll-back mechanism must be implemented in the processor pipeline to correct the error data read from the Razor SSRAM, which can be extravagant in a low-power processor. Yang et al [10] presented a double sensing mechanism with selective bitline voltage regulation (DS-SBVR) to improve the throughput of SSRAM, which can detect the timing error much earlier than Razor SSRAM. Shen et al [11] presented a TS cache based on the cross-sensing SSRAM, which reduces the area and the energy overhead by removing the capacitors required by DB-SBVR.…”

“…Due to the large area and energy overhead of the shared capacitors in DS-SBVR SRAM [10], RRS caches proposed in this paper are based on the cross-sensing SSRAM (CS-SSRAM) [11], whose structure is shown in Fig. 2.…”

“…Similarly, the area overhead for the Mixed-Cell is also 56.25% compared with the Perfect cache, which mainly comes from the 2X size cells in the robust ways and the parity bits in the remaining non-robust ways. According to [11], the area overhead of the CS-SSRAM is 3.4% in the 256 rows * 128 columns SRAM array, which is much lower than 13.18% of the DS-SBVR scheme [10]. By using the remapping scheme, every L1 tag entry needs 9 more bits to save RCs and the weak state (1.76%) in the tag array.…”

“…Since the energy of one reading operation is irrelative to the workloads, instead of collecting the whole energy consumption of the workloads, we only compare the energy consumed by one read operation by all approaches. The energy dissipation of one reading operation is collected from the simulations that using HSPICE at 0.5V 25 • C TT process corner with the SRAM arrays listed in Table 2, which is mainly consumed by SRAM arrays with the charging and the discharging of bitlines, voltage sensing, and error detecting [10]. Meanwhile, the energy consumed by the interconnection and buffers of the cache is counted as well.…”

“…For a more comprehensive comparison of all approaches we have discussed, this paper uses the normalized (to the Perfect cache) figure of merit (FOM) of latency, miss rate, area, and energy (LMAE) as Eq. 2, like the FOM of PPA in [10]. Note that the indicators in Eq.…”