A Double-Sampling Extended-Counting ADC

Maeyer, Jeroen De; Rombouts, Pieter; Weyten, L.

doi:10.1109/jssc.2003.822903

Cited by 40 publications

(11 citation statements)

References 21 publications

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“…Most analog circuit blocks are implemented with wellestablished switched-capacitor techniques and were partly reused from previous designs [16,17]. However the capacitive readout circuit requires special care, because it is likely to limit the noise-performance.…”

Section: Ct Readout Circuitmentioning

confidence: 99%

A Closed-Loop Digitally Controlled MEMS Gyroscope With Unconstrained Sigma-Delta Force-Feedback

et al. 2009

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In this paper we describe the system architecture and prototype measurements of a MEMS gyroscope system with a resolution of 0.025The architecture makes extensive use of control loops, which are mostly in the digital domain. For the primary mode both the amplitude and the resonance frequency are tracked and controlled. The secondary mode readout is based on unconstrained Σ∆ force-feedback, which does not require a compensation filter in the loop and thus allows more beneficial quantization noise shaping than prior designs of the same order. Due to the force-feedback, the gyroscope has ample dynamic range to correct the quadrature error in the digital domain. The largely digital set-up also gives a lot of flexibility in characterization and testing, where system identification techniques have been used to characterize the sensors. This way, a parasitic direct electrical coupling between actuation and readout of the mass-spring systems was estimated and corrected in the digital domain. Special care is also given to the capacitive readout circuit, which operates in continuous time.

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Section: Ct Readout Circuitmentioning

confidence: 99%

A Closed-Loop Digitally Controlled MEMS Gyroscope With Unconstrained Sigma-Delta Force-Feedback

et al. 2009

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“…However, high-order modulators are more prone to instability, and have a reduced non-overloading input range. As an alternative to single-loop modulators, multi-stage noise-shaping (MASH) IADCs [13], [14], and hybrid schemes which incorporate an added Nyquist-rate ADC to perform extended counting [9], [11], [15], [16] were proposed. However, MASH modulators and hybrid extended-counting schemes increase the circuit complexity, and circuit non-idealities may cause severe performance degradation.…”

Section: Introductionmentioning

confidence: 99%

A Micro-Power Two-Step Incremental Analog-to-Digital Converter

Chen

Zhang

et al. 2015

IEEE J. Solid-State Circuits

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Integrated sensor interface circuits require energy-efficient high-resolution data converters. This paper proposes a twostep incremental A/D converter (IADC) which extends the performance of an th-order IADC close to that of a th-order IADC. The implemented device uses the circuitry of a second-order IADC (IADC2) to achieve close to third-order SNR performance. The proposed circuit does not require very high opamp DC gain; the gain can be as low as 60 dB for 100 dB SNR data conversion. The implemented IADC achieves a measured dynamic range of 99.8 dB, and an SNDR of 91 dB for a maximum input 2.2 V and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm 2 , and it consumes only 10.7 µW. The measured FoMs are 0.76 pJ/conversion and 173.5 dB, both among the best reported results for IADCs. The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.Index Terms-Analog-to-digital converter (ADC), chopper stabilization, decimation filter, delta sigma ( ), extended-counting, flicker noise elimination, incremental data converters, low power, measurement and instrumentation, multi-stage noise shaping (MASH), multi-step, sensor interface, time-domain signal processing, two step.

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“…Since the oversampling ratio is limited to 128 for low power dissipation, a single-loop second-order incremental ADC cannot fulfill the design requirement. To increase the conversion accuracy and at the same time maintain good stability of the loop, the extended counting structure [4], [5] is used. Fig.…”

Section: Design Examplementioning

confidence: 99%

“…The maximum oversampling ratio is also limited by the input signal bandwidth, since low power dissipation is also an important consideration. By using a technique similar to extended counting in a two-step process [4]- [5], the resolution of IDCs can be improved significantly with low-order single-bit modulator and lower oversampling ratio. Calibration is also unnecessary for this architecture.…”

Section: Introductionmentioning

confidence: 99%