A double RESURF LDMOS with drain profile engineering for improved ESD robustness

Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design

“…The high-voltage MOSFET has been widely used as the common ESD protection device in the high-voltage CMOS ICs, because it can work as both of output driver and ESD protection device simultaneously without additional process modification. The earlier publications focused on analyzing and improving ESD robustness of the high-voltage MOSFET [3]- [6]. Although the double snapback characteristic in the n-p-n bipolar device for smart-power technology has been reported [1], however, the latchup-like failure from the high-voltage MOSFET as ESD protection device under normal circuit operating condition was not considered in the earlier reports.…”

Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device

“…Their weakness to the ESD stress is attributed to the extremely strong snapback, which results in current crowding and melting damage, non-uniform multi-finger triggering, and high latchup risk [1][2][3]. Extensive works have been devoted to achieve stable ESD protection performance, however ended with only limited successes [4][5][6][7].…”

ESD robustness improvement for integrated DMOS transistors —the different gate‐voltage dependence of It2 between VDMOS and LDMOS transistors

“…When ESD stress is applied to power device, it can clamp ESD voltage by triggering voltage ( V t1 ) that is higher than normal operation voltage and discharge ESD energy by using low impedance between holding point and second breakdown point. Therefore, we improved the power device to have higher second breakdown current [2–10].…”