A DLL with Jitter-Reduction Techniques for DRAM Interfaces

Abstract

Recently, demand has grown for high-bandwidth DRAMs to address high-capacity multimedia applications. A delay-locked loop (DLL) is a key component for achieving better timing margin in DRAM interfaces. A replica delay line in the DLL is susceptible to supply noise originating from switching noise in the DRAM core. Many solutions have been reported to improve the jitter performance of high-frequency clock under noisy environments [1,2]. This paper presents a jitter-immune DLL that suppresses the delay variation induced by the jitter of the replica delay line. The jitter reduction techniques control the loop behavior by monitoring the amount of jitter to optimize the jitter tolerance. This design also introduces a new architecture to generate I/Q phase, which has a wide operating range. Figure 27.6.1 shows the quadrature phase generation loop (QPGL). A differential input signal of 50% duty is needed to generate accurate Q and I phases. A differential pulse adjuster outputs two single-ended signals (DPA_p, DPA_n) with variable pulse width. The Q signal goes high at the rising edge of the DPA_p, and low at the rising edge of the DPA_n. The I signal becomes high at the falling edge of the DPA_p, and low at the falling edge of the DPA_n. The phase difference between Q and I is maintained at 90º through the feedback operation of the loop. The QPGL allows both coarse tuning and fine tuning. Coarse tuning selects an adequate range for the input frequency so that precise Q and I phases are produced in the fine tuning. When the V C exceeds the upper limit (V H ) or the lower limit (V L ), the rangeselection unit changes the range and resets the V C to V DD /2. In the graph showing the operating frequency versus V C , four fine tuning ranges overlap each other for the continuity of total tuning range. The QPGL achieves low jitter over a wide operating range because of lower gain in the fine tuning and the range switching by the coarse tuning. Figure 27.6.2 shows the structure of the differential pulse adjuster. The analog control voltage (V C ) is for the fine tuning and digital control bits (EN0, EN1) are for the coarse tuning. The falling transition by NMOS (MN1, MN2) is fast enough, and it is invulnerable to V C variation. On the other hand, the slope of the rising transition decreases as V C increases, because the resistance of MN3 and MN4 varies the amount of effective gate capacitance of MP1 and MP2 seen by the output node. As a result, the output signal has variable pulse width according to the value of the V C . The minimum value of the V C is above the threshold voltage of NMOS to prevent a lasting floating state at the PMOS gate node. Since the QPGL monitors the value of V C to select the operating range, the range of the V C has an upper and the lower limit that covers the threshold voltage limit. Figure 27.6.3 shows the block diagram of the proposed DLL. The duty cycle corrector (DCC) removes the duty distortion of the input. The QPGL generates the Q and I signal as well as digital bits (EN0, EN1) that define the...