A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

Kim, Byung-Guk; Kim, Lee-Sup; Park, Kwang-Il; Jun, Young-Hyun; Cho, Soo-In

doi:10.1109/jssc.2009.2016993

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Cited by 14 publications

(2 citation statements)

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“…By using these circuits require more power to lock the clocks. The other approach is synchronous mirror delay SMD [3][4][5][6][7][8] used for fast clock synchronization . It consume low power but it takes only narrow pulse clock signals.…”

Section: Introductionmentioning

confidence: 99%

Digital Clock Synchronization with Cyclic Rotation Algorithm

Rao¹

2013

IOSR-JVSP

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Section: Introductionmentioning

confidence: 99%

Digital Clock Synchronization with Cyclic Rotation Algorithm

Rao¹

2013

IOSR-JVSP

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“…The clock synchronization circuit is an important component in the system. Such circuits are used not only for moderately power-aware systems such as personal computers and servers, but also for severely power-aware ones like cellular phones and other portable applications [1]- [7]. The clock signal in a system might be disabled in hibernation mode in order to save power.…”

Section: Introductionmentioning

confidence: 99%

An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing

Cheng

Hong

Hsu

et al. 2012

IEEE Trans. VLSI Syst.

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This paper proposes an all-digital clock synchronization buffer (CSB) with one-cycle dynamic synchronization. The CSB synchronizes the input and output clocks in three clock cycles but maintains one cycle at fastest operating frequency. The CSB achieves one-cycle dynamic locking and synchronizes the dynamic frequencies with a modified structure. The CSB compensates for dynamic phase error with a modified fine-tuned circuit. The chip is fabricated using a 130-nm standard CMOS process. Its operating frequency range is between 300 MHz and 800 MHz. The power consumption and RMS jitter are 2.4 mW and 2.25 ps at 800 MHz, respectively. The active area of this chip is 0.015 mm .Index Terms-Arbitrary duty cycle, clock synchronization buffer (CSB), fast locking, one cycle dynamic locking, synchronous mirror delay (SMD).

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