A Dither-Less All Digital PLL for Cellular Transmitters

195

117

An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators' structures shows the proposed class-F exhibits the lowest phase noise at the same tank's quality factor and supply voltage. The prototype of the class-F oscillator is implemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of 136 dBc/Hz at 3 MHz offset from the carrier over 5.9-7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm while drawing 12 mA from 1.25 V supply.

Section: Introductionmentioning

confidence: 99%

A Class-F CMOS Oscillator

Babaie

Staszewski

2013

195

117

“…Summing σ 2 TD,out and σ 2 VD,out estimates σ 2 TAU,out , the overall time difference variance at the TAU output. Yet, we prefer to use the input-referred jitter for the PLL PN analysis, especially at the FREF side, e.g., [15] and [40]. According to (10) and ( 12), the transfer gain from FREF-related input, i.e., t S , to TAU's output is G TA = 8.…”

Section: Tau's Input-referred Noise and Its Contribution To Pll's Pha...mentioning

confidence: 99%

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Gao

Fritz

et al. 2023

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs-the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges-and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below −59 dBc. Under considerable supply or temperature variations, the worst spur still remains below −51.7 dBc without any background calibration tracking. Index Terms-Digital-to-time converter (DTC), fractional spur, phase-locked loop (PLL), process voltage and temperature (PVT), time-mode arithmetic unit (TAU). I. INTRODUCTIONT HE sub-sampling technique [1], [2], [3], [4], [5] and, more specifically, the narrow-range phase-detection concept [6], [7] have contributed to a significant improvement of phase noise (PN) in phase-locked loops (PLLs). Such techniques ensure that the phase detector (PD) can expect a

“…One approach is to connect the FCEs across the sources of the DCO's cross-coupled transistors [24], [59]. Another approach is to inductively couple the FCEs to the DCO tank [30].…”

Section: B Fine Frequency Control Elementsmentioning

confidence: 99%

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO

Venerus

Galton

2015

This paper presents the first published fully-integrated digital fractional-PLL based on a second-order frequency-to-digital converter (FDC) instead of a time-to-digital converter (TDC). The PLL's quantization noise is nearly identical to that of a conventional analog delta-sigma modulator based PLL ( -PLL). Hence, the quantization noise is highpass shaped and is suppressed by the PLL's loop filter to the point where it is not a dominant contributor to the PLL's output phase noise. However, in contrast to a -PLL, the new PLL has an entirely digital loop filter and its analog components are relatively insensitive to non-ideal analog circuit behavior. Therefore, it offers the performance benefits of a -PLL and the area and scalability benefits of a TDC-based digital PLL. Additionally, the PLL's digitally controlled oscillator (DCO) incorporates a new switched-capacitor frequency control element that is insensitive to supply noise and parasitic coupling. The PLL is implemented in 65 nm CMOS technology, has an active area of 0.56 mm , dissipates 21 mW from 1.0 and 1.2 V supplies, and its measured phase noise at 3.5 GHz is 123, 135, and 150 dBc/Hz at offsets of 1, 3, and 20 MHz, respectively. The PLL's power consumption is lower than previously published digital PLLs with comparable phase noise performance.