A Distributed Power Delivery Grid Based on Analog-Assisted Digital LDOs With Cooperative Regulation and IR-Drop Reduction

Lu, Yasu; Yang, Fan; Chen, Feng; Mok, Philip K. T.

doi:10.1109/tcsi.2020.2979336

Cited by 14 publications

(11 citation statements)

References 28 publications

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“…6. But, the IR drops induced across the on-chip parasitic resistances have become substantially large due to the increase in the power density of microprocessors over the past decade [54]. These IR drops can no longer be ignored during the design process in the ultra-deepsubmicron CMOS process, where the operating voltages are already very low.…”

Section: State-of-the-art Pdns a Distributed Heterogeneous Pdnmentioning

confidence: 99%

“…These IR drops can no longer be ignored during the design process in the ultra-deepsubmicron CMOS process, where the operating voltages are already very low. Energy losses and fluctuations associated with the IR drops are expected to be worse in the future as workloads in the CPU cores for cognitive computing and artificial intelligence becomes more heterogeneous and specialized [54]. To guarantee the performance in such workload conditions, the minimum supply voltage for the core must be larger than a critical voltage.…”

Section: State-of-the-art Pdns a Distributed Heterogeneous Pdnmentioning

confidence: 99%

“…To guarantee the performance in such workload conditions, the minimum supply voltage for the core must be larger than a critical voltage. Therefore, it requires a guardband above the critical voltage, causing an additional large power penalty [25], [54].…”

Section: State-of-the-art Pdns a Distributed Heterogeneous Pdnmentioning

confidence: 99%

“…Moreover, on-chip LDOs may also suffer from a slow loop latency, which results in a severe voltage drop during peak load transients, further requiring a larger V DD guardband. To address these challenges of the heterogeneous PDNs, a heterogeneous PDN with multiple distributed digital LDOs is proposed [54]. Digital LDOs can maintain a low dropout voltage of 40 -50 mV, offering a higher power efficiency as compared to their analog counterpart.…”

Section: State-of-the-art Pdns a Distributed Heterogeneous Pdnmentioning

confidence: 99%

“…Furthermore, by sharing the information with neighboring LDOs, the PDN can significantly enhance the transient response [54]. Fig.…”

Section: State-of-the-art Pdns a Distributed Heterogeneous Pdnmentioning

confidence: 99%

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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Conventional power delivery networks (PDNs) and power management techniques using off-chip power converters with bulky passive components cannot meet the ever-evolving power delivery requirements of high-performance modern system-on-chips (SoCs). In SoCs, heterogeneous components, including multi-core processors and mixed-signals peripheral circuits, require state-of-the-art PDNs to provide high-quality power-on-demand with minimum latency, simultaneously achieving the small-factor, high conversion efficiency, and minimum current consumption. To satisfy these power delivery requirements, various PDNs have been developed over the past decades, such as the conventional architectures using off-chip power converters, architectures using in-package power converters and fully-integrated power converters, and heterogeneous architectures (off-chip power converters and on-chip regulators). This paper reviews these architectural advancements of the PDNs and their advantages and limitations, which leads us to discuss a heterogeneous PDN structure consisting of a highly efficient off-chip switching-mode power converter and multiple highly precise small linear regulators integrated on chip at point-of-load locations. The heterogeneous PDN has been proved one of the most suitable architectures to achieve high-quality finegrained on-chip power delivery and management in SoCs. This paper also discusses unified voltage and frequency regulators (UVFRs), which support dynamic-variation-aware dynamic voltage and frequency scaling (DVFS) for fine-grained power management in multi-core processors. Based on the UVFR, we propose a modified heterogeneous PDN using frequency-referenced digital low-dropout regulators (FR-DLDOs) for more efficient DVFS, eliminating the need for band-gap circuits to provide reference voltages. As an exemplary implementation of FR-DLDO for this PDN, we present an FR-DLDO with a transientboost control, which accelerates the transient response. The transient-boost control is activated dynamically only when an abrupt change happens out of the steady state. The implemented FR-DLDO fabricated in a 40-nm CMOS process outperforms other FR-DLDOs in the figure-of-merit and peak power efficiency while driving 40 mA of load current. INDEX TERMS Power delivery network (PDN); fine-grained power management; dynamic-voltage and frequency scaling (DVFS); dynamic-voltage scaling (DVS); low-dropout regulator (LDO); digital LDO; unified-voltage and frequency regulator (UVFR); frequency-referenced digital LDO (FR-DLDO); transientboost control.

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Section: State-of-the-art Pdns a Distributed Heterogeneous Pdnmentioning

confidence: 99%

Section: State-of-the-art Pdns a Distributed Heterogeneous Pdnmentioning

confidence: 99%

Section: State-of-the-art Pdns a Distributed Heterogeneous Pdnmentioning

confidence: 99%

Section: State-of-the-art Pdns a Distributed Heterogeneous Pdnmentioning

confidence: 99%

“…Furthermore, by sharing the information with neighboring LDOs, the PDN can significantly enhance the transient response [54]. Fig.…”

Section: State-of-the-art Pdns a Distributed Heterogeneous Pdnmentioning

confidence: 99%

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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Architectural Advancement of Digital Low-Dropout Regulators

Akram

Hwang

2020

IEEE Access

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Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient finegrained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, eventdriven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

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Low-Voltage, Low-Area, nW-Power CMOS Digital-Based Biosignal Amplifier

et al. 2022

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This paper presents the operation principle and the silicon characterization of a power efficient ultralow voltage and ultra-low area fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA). Measured results in 180nm CMOS prototypes show that the proposed BioDIGOTA is able to work with a supply voltage down to 400 mV, consuming only 95 nW. Owing to its intrinsically highly-digital feature, the BioDIGOTA layout occupies only 0.022 mm 2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art, while keeping reasonable system performance, such as 7.6 NEF with 1.25 µV RMS input referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of CMRR and 55 dB of PSRR. INDEX TERMSUltra-Low Voltage (ULV) CMOS, Ultra-Low Power (ULP), Operational Transconductance Amplifier (OTA), Digital-Based Circuit, Internet of Things (IoT)

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A Distributed Power Delivery Grid Based on Analog-Assisted Digital LDOs With Cooperative Regulation and IR-Drop Reduction

Cited by 14 publications

References 28 publications

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Architectural Advancement of Digital Low-Dropout Regulators

Low-Voltage, Low-Area, nW-Power CMOS Digital-Based Biosignal Amplifier

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