A direct conversion RF front-end for 2-GHz WCDMA and 5.8-GHz WLAN applications

Hotti, M.; Kaukovuori, J.; Ryynänen, Jussi; Kivekas, K.; Jussila, J.; Halonen, K.

doi:10.1109/rfic.2003.1213890

Cited by 23 publications

(5 citation statements)

References 6 publications

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“…In particular, in low-gain mode (V CTRL = 3 V) the amount of current delivered to the resonant load depends on the emitter area ratio of transistors Q5-Q7 and Q6-Q8, while in high-gain mode (V CTRL = 0 V) the stage works as a traditional cascode LNA. The VG-LNA is 4 2 × (0.8 μm × 12 μm) Q 5 -Q 6 -Q 7 -Q 8 2 × (0.8 μm × 12 μm) MIXER Q 9 -Q 10 2 × (0.8 μm × 12 μm) Q 11 -Q 12 -Q 13 -Q 14 4 × (0.8 μm × 12 μm)…”

Section: Ir Down-converter Designmentioning

confidence: 99%

“…However, zero-IF down-converters are strongly affected by a high sensitivity to dc offsets, due to even-order distortions, local oscillator (LO) leakage and self-mixing, which limits their overall performance. Homodyne conversion was largely adopted for WLAN receivers [4][5][6][7][8], but recently an alternative heterodyne architecture was proposed to achieve a higher level of integration, while avoiding the drawbacks of the direct conversion. It exploits a sliding-IF rather than a traditional fixed-IF approach (i.e.…”

Section: Introductionmentioning

confidence: 99%

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An image-reject down-converter for 802.11a and HIPERLAN2 wireless LANs

2006

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An image-reject down-converter for IEEE 802.11a and ETSI HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-f T silicon bipolar process. The circuit integrates a variable-gain low noise amplifier and a double-balanced mixer along with passive image rejection filters. It exhibits a 4-dB noise figure and a power gain of 23 dB. By reducing the low noise amplifier gain by 9 dB (thanks to a 1-bit gain control), the down-converter achieves an input 1-dB compression point of -14 dBm, while drawing only 23 mA from a 3-V supply voltage. The adopted filtering approach provides an image rejection ratio higher than 60 dB.

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Section: Ir Down-converter Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An image-reject down-converter for 802.11a and HIPERLAN2 wireless LANs

2006

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“…The second category uses reconfigurable mixer together with multiple LNAs [4], [5]. The Third approach mixes the first two approaches together [6].…”

Section: Introductionmentioning

confidence: 99%

A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting Noise Cancellation

Amer

Hegazi

Ragaie

2007

IEEE J. Solid-State Circuits

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This paper describes the design and implementation of a wideband merged LNA and mixer chip covering the frequency range from 0.1 to 3.85 GHz using 90-nm CMOS technology. Its high level of integration as well as its low power consumption makes it suitable for the rapidly growing software defined radio RF receivers. The chip performance achieves S11 below 10 dB along the entire band and a minimum single side band noise figure of 8.4 dB at IF frequency of 70 MHz. Power conversion gain is measured to be 12.1 dB while the input referred 1 dB compression point is measured to be 12.8 dBm. The chip core consumes only 9.8 mW from a 1.2 V supply with a die area, including the pads, of 0.88 mm 2 .Index Terms-Low noise, merged LNA and mixer, multi-standard, noise cancellation, software defined radio, wideband receiver.

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“…And as the 3G and 4G technologies are introduced, the evolution of wireless communication standards is much accelerated; thus multi-standard transceiver is needed for smooth migration between them. Moreover, many performances such as low power consumption, high data rate, and mobility should be satisfied simultaneously [1]. To meet the market needs, reconfigurable transceiver technologies which can cover different carrier frequencies and bandwidths are being studied to meet whole requirements.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable CMOS Power Amplifier Operating from 0.9 TO 2.4 GHZ for WPAN Application

Yun¹,

Yoo²

2006

2006 IEEE International SOC Conference

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A reconfigurable CMOS power amplifier for WPAN application is designed in CMOS 0.25 um technology. It is composed of driver stage, power stage, interstage matching, and output matching stages. Power amplifier can be operated in various frequencies by controlling interstage matching and has the characteristic at required frequencies. The proposed power amplifier has 42~57 % power added efficiency and 21.8~27.5 dB gain characteristic at frequencies of 0.9~2.4 GHz with 20 dBm output power.

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A direct conversion RF front-end for 2-GHz WCDMA and 5.8-GHz WLAN applications

Cited by 23 publications

References 6 publications

An image-reject down-converter for 802.11a and HIPERLAN2 wireless LANs

An image-reject down-converter for 802.11a and HIPERLAN2 wireless LANs

A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting Noise Cancellation

A Reconfigurable CMOS Power Amplifier Operating from 0.9 TO 2.4 GHZ for WPAN Application

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