A Digital Readout Integrated Circuit Based on Pixel-Level ADC Incorporating On-Chip Image Algorithm Calibration for IRFPA

Yan, Zeng; Yang, Shiheng; Liu, Yueduo; Bao, Rongxin; Zhu, Zihao; Lin, Jiahui; Zhou, Xiong; Chen, Yong; Yin, Jun; Mak, Pui-In; Li, Qiang

doi:10.1109/jsen.2023.3300874

Cited by 2 publications

(1 citation statement)

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“…In [ 7 , 8 , 9 ], small-pixel digital sensors provide advantages in reducing the size, weight, and power (SWaP), improving noise immunity, simplifying interfacing requirements, and lessening susceptibility to electromagnetic interference (EMI). DROIC, which is based on pixel-level ADC, directly accomplishes analog-to-digital conversion in a pixel array [ 10 , 11 , 12 , 13 ]. However, this form of pixel-level ADC is only suited for usage in large-sized pixels.…”

Section: Introductionmentioning

confidence: 99%

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit

Hu,

Yao,

Chen

et al. 2024

Sensors

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This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of −0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital).

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