A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications

Yun, Seong Jin; Lee, Jiseong; Im, Yun Chan; Kim, Yong Sin

doi:10.1109/tvlsi.2019.2920910

Cited by 10 publications

(2 citation statements)

References 17 publications

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“…The measured PSRR is better than -30dB at low frequencies, while the lowest PSRR is -8.5dB at 20MHz. Table I summarizes the performance of the proposed LDO and compares it with state-of-the-art LDOs with the standard figure of merit (FoM) and process-scaled FoM′ [20]. The proposed LDO achieves the lowest FoM′ among the stateof-the-art LDOs.…”

Section: Circuit Implementation and Experimental Resultsmentioning

confidence: 99%

A Hybrid Low-Dropout (LDO) Regulator Using a Load Replication Circuit for DRAM Cores

et al. 2022

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This paper presents a cost-effective hybrid low drop-out regulator (LDO) circuitry for state-ofthe-art DDR DRAM cores that not only supports various refresh operations, but also meets the JEDEC specification of the refresh period by improving the load-transient response. In order to guarantee a stable output voltage by achieving the precise off-control operation, a load replication circuit with dummy DRAM cells is exploited. The proposed cost-effective LDO has been implemented and fabricated in a standard 180nm CMOS technology and occupies 0.165mm 2 . By adopting the hybrid LDO, voltage droop improvements of 62mV and 110mV, and tRFC gain of 100ns and 120ns are measured with refresh rates of 4K and 8K, respectively. The measured current consumption overhead by 8 hybrid LDOs is 36μA during the 8K refresh operation. The peak current efficiency is 99.6% at a supply voltage of 1.2V.INDEX TERMS Double data rate (DDR), DRAM cores, low drop-out regulator, hybrid LDO, load replication, load-transient response.

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Section: Circuit Implementation and Experimental Resultsmentioning

confidence: 99%

A Hybrid Low-Dropout (LDO) Regulator Using a Load Replication Circuit for DRAM Cores

et al. 2022

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“…The hybrid synchronous-asynchronous architecture was employed in [18,19,20] to improve the transient response and regulation precision. The selfclocked technique was employed in [21,22], which eliminates the need for an external high-speed clock and achieves fast transient response. A hybrid LDO is proposed in [23,24,25,26] to achieve fast setting time and good power supply ripple rejection.…”

Section: Introductionmentioning

confidence: 99%

A self-clocked binary-seaching digital low-dropout regulator with fast transient response

Shi

Zhao

Tang

et al. 2020

IEICE Electron. Express

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A self-clocked binary-searching (SCBS) digital low-dropout (DLDO) regulator with fast transient response is proposed. The SCBS controller employed in the DLDO achieves fast transient response and eliminates the need for an external high-speed clock. A transient enhancement unit (TEU) is proposed to reduce the undershoot of the output voltage. The proposed DLDO is simulated in a 40-nm CMOS process with an active area of 0.015 mm 2 . The simulation results show that with a 15.5mA/2ns load step, it shows a setting time of 28 ns with a voltage undershoot of 93 mV, and it achieves a peak current efficiency of 99.87% by consuming a 19.4-μA quiescent current. Thus, the resulting FOM 1 is 0.379 ps and FOM 2 is 5 ps.

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Architectural Advancement of Digital Low-Dropout Regulators

Akram

Hwang

2020

IEEE Access

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Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient finegrained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, eventdriven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

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A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications

Cited by 10 publications

References 17 publications

A Hybrid Low-Dropout (LDO) Regulator Using a Load Replication Circuit for DRAM Cores

A Hybrid Low-Dropout (LDO) Regulator Using a Load Replication Circuit for DRAM Cores

A self-clocked binary-seaching digital low-dropout regulator with fast transient response

Architectural Advancement of Digital Low-Dropout Regulators

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