A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells

Abstract

Submicrometer static random access memory cells are more susceptible to particle strike soft errors and increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, analytical models for the critical charge variations accounting for both die-to-die and within-die variations are proposed. The derived models are verified and compared to Monte Carlo simulations by using industrial 65-nm CMOS technology. This paper provides new design insights such as the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability, especially, at lower supply voltages. It demonstrates that two extreme values of this coupling capacitor exist. The first value results in maximum relative variations and the other results in minimum relative variations. Therefore, the circuit designers can utilize these results to design the coupling capacitor to limit the variations under power and performance constraints in early design cycles. The derived analytical models account for the impact of the supply voltage and different particle strike conditions. These results are particularly important for soft error tolerant and variation tolerant designs in submicrometer technologies, especially, for low power operations.Index Terms-Deep submicrometer, process variations, reliability, soft errors, static random access memory (SRAM).

Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells

“…1) is the most susceptible to particle strikes. It has been reported that of a 0-to-1 flip in SRAM is about 22X larger than that for a 1-to-0 flip [10], [24]. When a particle strike occurs at node , the injected current pulls this node voltage down to "0" against the pMOS transistor current which tries to recover the node voltage.…”

“…Due to NBTI, current is reduced due to the increased which reduces and increases the SER. In [10], the sensitivity of to transistor threshold voltage, , is given by:…”

“…Similarly, due to the current mirror action between transistors Md4 and Md12, the voltage is . Since transistors Md6, Md7, Md10, and Md11 are matched, the two output voltages, and , are given by (10) These two output voltages, and , have an equal common mode voltage, . When these two output voltages are applied to the basic squaring circuit, the resultant output voltage, , is given by [31] (11)…”

“…The simulations are performed with ps and is varied in SPICE transient simulations to find the value of that results in cell flipping. Then, is calculated by using the following [10]: (13) where is the cell flipping time. Fig.…”

“…This increase not only leads to reduced temporal performance but also causes reliability degradation and potential device failure [9]. Typically, this increase results in increasing the SRAM SER (because it decreases the strength of the SRAM pMOS transistors which reduces [10]), reducing the SRAM static noise margin (SNM) [11], [12], and increasing the read failure probability which results in SRAM yield loss [12].…”