A design of transponder IC for highly collision resistive RFID systems

Fukumizu, Yohei; Nagata, Makoto; Ohno, Shuji; Taki, Kazuo

doi:10.1109/apasic.2004.1349527

Cited by 9 publications

(5 citation statements)

References 1 publication

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“…Compared with the power consumptions given by Refs. [8,[10][11][12] and our simulation results for a 0.18 µm process, our design exhibits ultralow power consumption. In addition, the power consumption will be optimized further with more advanced technology, as shown in Table 1.…”

Section: Ip Ownermentioning

confidence: 69%

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Design of an ultra-low-power digital processor for passive UHF RFID tags

Wanggen

Zhang

et al. 2009

J. Semicond.

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A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 µm process of Chartered Semiconductor.

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Section: Ip Ownermentioning

confidence: 69%

“…Masui [10] Abrial [8] Usami [11] Fukumizu [12] consumption. These methods include clock gating at system level, a ripple counter, and a low operating voltage.…”

Section: Ip Ownermentioning

confidence: 99%

Design of an ultra-low-power digital processor for passive UHF RFID tags

Wanggen

Zhang

et al. 2009

J. Semicond.

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“…The power is 3.15 mW with the average current of 2.1 mA @1.5 V. Compared with that in Refs. [8,[10][11][12], our design can implement complex function with lower power dissipation, as shown in Table 1, achieving our expected object.…”

Section: Design Implementation and Verificationmentioning

confidence: 81%

“…Recently, most baseband-processors choose the CPU architecture [8][9][10][11], and almost do not analyze the characteristics of protocol processing or develop special circuits [12]. However, based on the characteristic of protocol processing and special low-power demands, this paper proposes a new architecture with power management scheme, and also presents a novel method of partial-decoding and a new scheme of generating 16-bits pseudo-random numbers.…”

Section: Introductionmentioning

confidence: 99%

An ultra low-voltage, low-power baseband-processor for UHF RFID tag

Jianyun

Min

2008

Front. Electr. Electron. Eng. China

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A novel ultra low-voltage, low-power basebandprocessor for UHF radio frequency identification (RFID) tag is presented here. The baseband-processor is compatible with the EPC TM class-1 generation-2 (C1G2) UHF RFID protocol, and fits the requirements of ultra lowpower of passive tags. Based on the analysis of the special power consumption of the tag, a new architecture is proposed. A novel scheme for generating pseudo-random numbers as well as a new method of partial-decoding is developed. Besides, other low-power techniques are also adopted for the special baseband-processor which implements complex functions, such as encoding/coding, anticollision and authorization scheme, and reading/writing operation to EEPROM. The chip was fabricated in 0.35 mm 1P3M standard CMOS process. Experimental results show that it achieves low power operation of 3.15 mW @ 1.5 V with the core area of 1.1 mm 6 0.8 mm.

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“…"#$ %P & Aloha [2] I ALOHA [3] I*+ ALOHA [4] I*+:'- [5] I3/0 [6] I*+3/0 [7] YN OS,# P(!) CDMA K*) SDMA + [8] N,-0./!01D …”

mentioning

confidence: 99%

An Anti-Collision Algorithm Based on Subset-division and Dynamic Matching Mechanism for Intelligent Tags

Cao

Zhou

2006

2007 Chinese Control Conference

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A collision will occur when more than one tag is read by the reader in the RFID system. The Slotted Aloha algorithm is presented to solve tag collision problem. But it has some deficiencies when the number of tags is great. An anti-collision algorithm based on subset-division and dynamic-matching mechanism was presented to advance it in this work. It divided the intelligent tags into different subsets according to time-slices and adjusted dynamically the matching area to reduce the collision probabilities. The simulation results show that compared with slotted aloha, the new anti-collision algorithm enhances obviously the identifying efficiency, success-identifying rate and throughput, and its success-identifying rate can reach 95% even though the number of tags is great. It takes on better application value.

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A design of transponder IC for highly collision resistive RFID systems

Cited by 9 publications

References 1 publication

Design of an ultra-low-power digital processor for passive UHF RFID tags

Design of an ultra-low-power digital processor for passive UHF RFID tags

An ultra low-voltage, low-power baseband-processor for UHF RFID tag

An Anti-Collision Algorithm Based on Subset-division and Dynamic Matching Mechanism for Intelligent Tags

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