A depth-first-search controlled gridless incremental routing algorithm for VLSI circuits

Abstract

In the engineering change order (ECO) process, engineers make changes to VLSI circuits after their layouts are completed in order to correct electrical problems or design errors. As far as routing is concerned, in order to capitalize on the enormous resources and time already spent on routing the circuit, and to meet time-to-market requirements, it is desirable to reroute only the ECO-affected portion of the circuit, while minimizing any routing changes in the larger unaffected part of the circuit in order to preserve its electrical properties. In this paper, we develop a novel algorithm to find incremental routing solutions using a gridless framework for VLSI circuits that require variable width and variable spacing on interconnects. The basic idea in our algorithm is to route the new or ECO-modified nets by minimally rearranging , if necessary, some portions of some existing nets using a novel DFS controlled process that does not allow the perturbed existing nets' lengths and topologies to change beyond pre-set limits. With these constraints, it explores a number of low-cost ways of rerouting the portions of these nets within the available routing resources (2 metal layers only). Experimental results show that within the above constraints our incremental router succeeds in routing more than 98% of ECO-generated nets, and also that its failure rate is 5 to 12 and 2.4 to 9 times less than that of previous incremental routing techniques Standard (Std) and Rip-up&Reroute (R&R), respectively. It is also able to route most of the wide nets using a reasonable number of vias and with near-minimal net lengths.

Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations

“…To find a solution for the originally bumped o-seg, we thus perform a depth first search (DFS) of interconnect bumps-andreroutes; the core non-TD DFS algorithm for this process is developed in detail in [5]. This DFS tree terminates successfully if all its leaf nodes represent non-overlapped routes for the last o-segs on each path in the tree.…”

“…An incremental routing algorithm for FPGAs that uses a bump-and-refit (B&R) approach which routes the new nets by "bumping" less critical existing nets in a controlled manner and without changing their topologies was proposed in [4] and was extended for ECO routing and for FPGAs with complex switchboxes in [3]. Finally, the algorithm presented in [5] uses a depth-first search (DFS) controlled B&R process to find good-quality incremental routing solutions using a gridless framework for VLSI circuits that require variable width and variable spacing on interconnects.…”

“…Past work tackling the incremental routing problem include [1,2,3,4,5,10]. In [1], re-routing is done in a standard singlenet routing mode in the available routing space without disturbing existing net routes; we term this incremental routing approach Standard (Std).…”

“…We have developed a novel technique in which only local slack-related information is used in determining if segment re-routes of nets or new pin connections satisfy all slack constraints of the net. We also use a depthfirst-search (DFS) control similar to [5], in order to route the new nets by minimally perturbing 1 existing nets, but with the added (non-trivial) constraint of satisfying all slack constraints.…”

Research accomplishments

“…Incremental routing is used for engineering-change-order (ECO) applications and fault reconfiguration. Use of this novel concept has resulted in significantly better results in terms of routing completion rates, wire-lengths and viausage than previous ripup-and-reroute approaches for both FPGA and ASICs [9,44,54]. Further novel concepts including that of Steiner-node slack tolerances were introduced in [41] to yield a near-wirelength optimal and guaranteed slack-satisfying timing-driven incremental routing method TIDE for ASICs that also obtains significant improvements over ripup-and-reroute approaches in the timing-driven context (e.g., 4-6 times fewer slack violations) while being about three times faster.…”