A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal

Galton, I.; Huff, W.; Carbone, Paolo; Siragusa, E.

doi:10.1109/4.735546

Cited by 22 publications

(8 citation statements)

References 15 publications

(23 reference statements)

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“…The architecture was refined and rigorously analyzed in [49], and the first IC implementation was published in [50]. The version of the FDC used in this work is shown in Fig.…”

Section: B Frequency-to-digital Convertermentioning

confidence: 99%

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO

Venerus

Galton

2015

IEEE J. Solid-State Circuits

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This paper presents the first published fully-integrated digital fractional-PLL based on a second-order frequency-to-digital converter (FDC) instead of a time-to-digital converter (TDC). The PLL's quantization noise is nearly identical to that of a conventional analog delta-sigma modulator based PLL ( -PLL). Hence, the quantization noise is highpass shaped and is suppressed by the PLL's loop filter to the point where it is not a dominant contributor to the PLL's output phase noise. However, in contrast to a -PLL, the new PLL has an entirely digital loop filter and its analog components are relatively insensitive to non-ideal analog circuit behavior. Therefore, it offers the performance benefits of a -PLL and the area and scalability benefits of a TDC-based digital PLL. Additionally, the PLL's digitally controlled oscillator (DCO) incorporates a new switched-capacitor frequency control element that is insensitive to supply noise and parasitic coupling. The PLL is implemented in 65 nm CMOS technology, has an active area of 0.56 mm , dissipates 21 mW from 1.0 and 1.2 V supplies, and its measured phase noise at 3.5 GHz is 123, 135, and 150 dBc/Hz at offsets of 1, 3, and 20 MHz, respectively. The PLL's power consumption is lower than previously published digital PLLs with comparable phase noise performance.

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“…The architecture was refined and rigorously analyzed in [49], and the first IC implementation was published in [50]. The version of the FDC used in this work is shown in Fig.…”

Section: B Frequency-to-digital Convertermentioning

confidence: 99%

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO

Venerus

Galton

2015

IEEE J. Solid-State Circuits

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“…Let be a real continuous-time message signal such that , , for some positive constant . Frequency modulation with frequency deviation consists of forming the frequency modulated carrier (1) where the angle of the modulated signal is (2) for simplicity we assume that the angle of the modulated wave is zero at . We also have assumed a causal message signal, for .…”

Section: Systemmentioning

confidence: 99%

“…Straightforward multibit quantization and potentially higher sampling frequency compared to second-order MASH delta-sigma modulators, are two amongst other features this new provides. The frequency-to-digital concept of this modulator is as in [2], but with a different approach. While [2] uses a discrete-time phase-locked loop (PLL) to perform frequency-to-digital conversion, the second-order MASH-like is based on the simple, nonfeedback first-order solution.…”

Section: Introductionmentioning

confidence: 99%

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Adaptive correction of errors in second-order MASH ΔΣFDM solution

Finsrud

Høvin

Lande

2001

IEEE Trans. Circuits Syst. II

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In many communication applications, it is necessary to demodulate and digitize frequency or phase modulated signals. This paper presents a new, adaptive improvement to a novel second-order frequency-to-digital cascaded delta sigma modulator. The adaptive corrections significantly reduce the sensitivity to analog imperfections in the MASH-like 16 frequency-to-digital modulator, and makes it possible to implement the circuit in standard digital CMOS without loosing performance. The result is a simple second-order delta-sigma modulator with high precision. Simulations of the circuit with errors and corrections are included to confirm the theory.

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“…Another version of frequency-to-digital converter proposed by Galton et al [36]- [39] is shown in Fig. 4-24.…”

Section: Frequency-to-digital Conversionmentioning

confidence: 99%