A delay model and speculative architecture for pipelined routers

Peh, Li-Shiuan; Dally, William J.

doi:10.1109/hpca.2001.903268

Cited by 389 publications

(305 citation statements)

References 6 publications

Supporting

Mentioning

302

Contrasting

Order By: Relevance

“…The ubiquitous adoption of the system-on-chip (SoC) paradigm and the need for high bandwidth communication links between different modules have led to a number of interesting proposals targeting high-speed network switches/routers [13,28,29,30,31]. This section provides a brief overview of router complexity and different pipelining options available.…”

Section: Router Modelsmentioning

confidence: 99%

See 1 more Smart Citation

Interconnect design considerations for large NUCA caches

MuralimanoharNaveen

BalasubramonianRajeev

2007

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposals advocate splitting the cache into a large number of banks and employing a network-on-chip (NoC) to allow fast access to nearby banks (referred to as Non-Uniform Cache Architectures -NUCA). Most studies on NUCA organizations have assumed a generic NoC and focused on logical policies for cache block placement, movement, and search. Since wire/router delay and power are major limiting factors in modern processors, this work focuses on interconnect design and its influence on NUCA performance and power. We extend the widely-used CACTI cache modeling tool to take network design parameters into account. With these overheads appropriately accounted for, the optimal cache organization is typically very different from that assumed in prior NUCA studies. To alleviate the interconnect delay bottleneck, we propose novel cache access optimizations that introduce heterogeneity within the inter-bank network. The careful consideration of interconnect choices for a large cache results in a 51% performance improvement over a baseline generic NoC and the introduction of heterogeneity within the network yields an additional 11-15% performance improvement.

show abstract

Section: Router Modelsmentioning

confidence: 99%

“…The pipeline depth ranges from a single cycle speculative model [29] to an eight stage model in the Alpha 21364 [28]. For the purpose of our study, we adopt the moderately aggressive implementation with a 3-stage pipeline [30]. Our power model is also derived from a corresponding analysis by some of the same authors [36].…”

Section: Router Modelsmentioning

confidence: 99%

Interconnect design considerations for large NUCA caches

MuralimanoharNaveen

BalasubramonianRajeev

2007

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

show abstract

“…We have considered the research in the area, like Peh's work [14], which indicates that the arbitration time is logarithmic in the number of VCs. In Table 1, the number before the slash is the delay for 8 VC switches and the number after the slash is the delay for 2 VC switches (both traditional and using our technique).…”

Section: Simulated Architecturementioning

confidence: 99%

Providing Full QoS Support in Clusters Using Only Two VCs at the Switches

Martínez

Alfaro

Sánchez

et al. 2005

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. Current interconnect standards providing hardware support for quality of service (QoS) consider up to 16 virtual channels (VCs) for this purpose. However, most implementations do not offer so many VCs because they increase the complexity of the switch and the scheduling delays. In this paper, we show that this number of VCs can be significantly reduced. Some of the scheduling decisions made at network interfaces can be easily reused at switches without significantly altering the global behavior. Specifically, we show that it is enough to use two VCs for QoS purposes at each switch port, thereby simplifying the design and reducing its cost.

show abstract

“…Such designs will fragment segments into bit-level signals and weaken the results of our reduction. In our experimental results, the high-performance router [8] is such a design. Without this preprocessing no netlist reduction is possible.…”

Section: Implementing the Reductionmentioning

confidence: 93%

“…Our final benchmark is a pipelined high-performance router created at Stanford [8]. The router has four port connections to adjacent routers plus an inject node and an eject node.…”

Section: Resultsmentioning

confidence: 99%

A Practical Approach to Word Level Model Checking of Industrial Netlists

Bjesse

Computer Aided Verification

View full text Add to dashboard Cite

Abstract. In this paper we present a word-level model checking method that attempts to speed up safety property checking of industrial netlists. Our aim is to construct an algorithm that allows us to check both bounded and unbounded properties using standard bit-level model checking methods as back-end decision procedures, while incurring minimum runtime penalties for designs that are unsuited to our analysis. We do this by combining modifications of several previously known techniques into a static abstraction algorithm which is guaranteed to produce bit-level netlists that are as small or smaller than the original bitblasted designs. We evaluate our algorithm on several challenging hardware components.

show abstract

A delay model and speculative architecture for pipelined routers

Cited by 389 publications

References 6 publications

Interconnect design considerations for large NUCA caches

Interconnect design considerations for large NUCA caches

Providing Full QoS Support in Clusters Using Only Two VCs at the Switches

A Practical Approach to Word Level Model Checking of Industrial Netlists

Contact Info

Product

Resources

About