A deeply pipelined and parallel architecture for denoising medical images

Abstract

In this paper we present an almost automatic synthesis of a highly complex, throughput optimized architecture of an adaptive multiresolution filter as used in medical image processing for FPGAs. The filter consists of 16 parallel working modules, where the most computationally intensive module achieves software pipelining of a factor of 85, that is, computations of 85 iterations overlap each other. By applying a state-of-the-art high-level synthesis tool, we show that this approach can be used for real world applications. In addition, we show that our highlevel synthesis tool is capable of significantly reducing the well known productivity gap of embedded system design by almost two orders of magnitude. Finally, we can conclude that the FPGA implementation of the multiresolution image processing algorithm is far ahead of a comparable implementation for graphics cards in terms of power efficiency.

Invasive Tightly-Coupled Processor Arrays

“…The scheduling method incorporates module selection (e.g., a mov operation can be performed by an adder or a multiplier unit), software pipelining, and runtime-dependent conditions. Although it is a well-known fact that MIP is NPhard, the application of this scheduling technique to complex algorithms with more than 380 statements in a loop body was demonstrated in Hannig et al [2010] for nonprogrammable hardware accelerators.…”

Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution

“…PARO [11], for instance, is a HLS environment for the domain of image processing and provides domain-specific augmentations for border treatment and reductions such as median filtering. It is also capable of adaptive multiresolution filtering in medical imaging [12].…”