Invasive Tightly-Coupled Processor Arrays

Hannig, Frank; Lari, Vahid; Boppu, Srinivas; Tanase, Alexandru; Reiche, Oliver

doi:10.1145/2584660

Cited by 59 publications

(2 citation statements)

References 37 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [110], the authors proposed mapping of CNNs onto Tightly Coupled Processor Array (TCPA) efficiently. TCPA belongs to the class of CGRA, containing an array of tightly coupled VLIW Processing Elements (PEs) [104]. TCPA offers multiple levels of parallelism, for instance, task-level, loop-level, iteration-level, instruction-level parallelism, etc.…”

Section: Cgra-based Acceleratorsmentioning

confidence: 99%

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

et al. 2022

Self Cite

View full text Add to dashboard Cite

In the modern-day era of technology, a paradigm shift has been witnessed in the areas involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL). Specifically, Deep Neural Networks (DNNs) have emerged as a popular field of interest in most AI applications such as computer vision, image and video processing, robotics, etc. In the context of developed digital technologies and the availability of authentic data and data handling infrastructure, DNNs have been a credible choice for solving more complex real-life problems. The performance and accuracy of a DNN is a way better than human intelligence in certain situations. However, it is noteworthy that the DNN is computationally too cumbersome in terms of the resources and time to handle these computations. Furthermore, general-purpose architectures like CPUs have issues in handling such computationally intensive algorithms. Therefore, a lot of interest and efforts have been invested by the research fraternity in specialized hardware architectures such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), and Coarse Grained Reconfigurable Array (CGRA) in the context of effective implementation of computationally intensive algorithms. This paper brings forward the various research works on the development and deployment of DNNs using the aforementioned specialized hardware architectures and embedded AI accelerators. The review discusses the detailed description of the specialized hardware-based accelerators used in the training and/or inference of DNN. A comparative study based on factors like power, area, and throughput, is also made on the various accelerators discussed. Finally, future research and development directions, such as future trends in DNN implementation on specialized hardware accelerators, are discussed. This review article is intended to guide hardware architects to accelerate and improve the effectiveness of deep learning research.INDEX TERMS Machine learning, field programmable gate array (FPGA), deep neural networks (DNN), deep learning (DL), application specific integrated circuits (ASIC), artificial intelligence (AI), central processing unit (CPU), graphics processing unit (GPU), hardware accelerators. FIGURE 3. A single ANN neuron with its elements (inputs, weights, bias, summer, activation function, and output).

show abstract

Section: Cgra-based Acceleratorsmentioning

confidence: 99%

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

et al. 2022

Self Cite

View full text Add to dashboard Cite

show abstract

“…Along the same line, modern platforms also incorporate heterogeneous processing resources to cater to the specific functional and non-functional requirements of applications from different domains of computing, see, for example, Reference [6]. In addition to the current practice of integrating various types of general-purpose cores on a chip, many-core platforms are also on the verge of incorporating domain/application-specific processing resources, for example, Digital Signal Processor (DSP) cores for signal/image processing [7], Graphics Processing Units (GPUs) for graphics processing and AI acceleration in deep learning [8,9], and Coarse-Grained Reconfigurable Arrays (CGRA) for the acceleration of (nested-)loops [10,11]. Moreover, Field Programmable Gate Arrays (FPGAs) have also been incorporated to provide a reconfigurable fabric for hardware acceleration [9,12].…”

Section: Introductionmentioning

confidence: 99%

Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective

Pourmohseni

Glaß

Henkel

et al. 2020

JLPEA

View full text Add to dashboard Cite

Many-core platforms are rapidly expanding in various embedded areas as they provide the scalable computational power required to meet the ever-growing performance demands of embedded applications and systems. However, the huge design space of possible task mappings, the unpredictable workload dynamism, and the numerous non-functional requirements of applications in terms of timing, reliability, safety, and so forth. impose significant challenges when designing many-core systems. Hybrid Application Mapping (HAM) is an emerging class of design methodologies for many-core systems which address these challenges via an incremental (per-application) mapping scheme: The mapping process is divided into (i) a design-time Design Space Exploration (DSE) step per application to obtain a set of high-quality mapping options and (ii) a run-time system management step in which applications are launched dynamically (on demand) using the precomputed mappings. This paper provides an overview of HAM and the design methodologies developed in line with it. We introduce the basics of HAM and elaborate on the way it addresses the major challenges of application mapping in many-core systems. We provide an overview of the main challenges encountered when employing HAM and survey a collection of state-of-the-art techniques and methodologies proposed to address these challenges. We finally present an overview of open topics and challenges in HAM, provide a summary of emerging trends for addressing them particularly using machine learning, and outline possible future directions. While there exists a large body of HAM methodologies, the techniques studied in this paper are developed, to a large extent, within the scope of invasive computing. Invasive computing introduces resource awareness into applications and employs explicit resource reservation to enable incremental application mapping and dynamic system management.

show abstract

*‐Predictable MPSoC execution of real‐time control applications using invasive computing

Brand

Witterauf

Sousa

et al. 2019

Concurrency and Computation

Self Cite

View full text Add to dashboard Cite

Summary The fulfillment of non‐functional requirements like timing or energy consumption is of utmost importance in many embedded systems and respective applications. Especially, with the introduction of multi‐core architectures, the ability to predict non‐functional execution qualities becomes more and more difficult, as multiple concurrent application programs may interfere in execution when typically sharing all the resources. In this paper, we advocate a novel parallel computing paradigm called invasive computing that allows to isolate application programs on multi‐core targets. For a presented case study of a cyber‐physical real‐time control system, we show that invasive computing enables composability that in fact allows to characterize and analyze each application program statically and independent from each other. More specifically, it is shown that a distributed object detection algorithm for controlling an inverted pendulum and implemented on a heterogeneous invasive multi‐processor SoC (MPSoC) is able to provide real‐time guarantees as well as reliability requirements on demand.

show abstract

Invasive Tightly-Coupled Processor Arrays

Cited by 59 publications

References 37 publications

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective

*‐Predictable MPSoC execution of real‐time control applications using invasive computing

Contact Info

Product

Resources

About