2009
DOI: 10.1007/s00138-009-0190-2
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A dedicated hardware architecture for real-time auto-focusing using an FPGA

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Cited by 8 publications
(6 citation statements)
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“…Although the contrast computation is a little more complex than CMSL, the computation time is acceptable and will not cause any lag in our passive AF system. In addition, the dedicated hardware architecture for real-time auto-focusing, such as field programmable gate array (FPGA)-based AF system [ 34 ], can be used to shorten the computation time, which processes the incoming pixels simultaneously with their neighboring pixels based on its parallelized window processing architecture. The extra computation in CMAN aims to distinguish the best focused peak from noise influence which is critical to ensure the focusing accuracy and reliability.…”
Section: Proposed Passive Af Algorithmmentioning
confidence: 99%
“…Although the contrast computation is a little more complex than CMSL, the computation time is acceptable and will not cause any lag in our passive AF system. In addition, the dedicated hardware architecture for real-time auto-focusing, such as field programmable gate array (FPGA)-based AF system [ 34 ], can be used to shorten the computation time, which processes the incoming pixels simultaneously with their neighboring pixels based on its parallelized window processing architecture. The extra computation in CMAN aims to distinguish the best focused peak from noise influence which is critical to ensure the focusing accuracy and reliability.…”
Section: Proposed Passive Af Algorithmmentioning
confidence: 99%
“…LT on a parallel computer (Mitrion Virtual Processor) should run in a pipeline manner and take advantage of FPGA parallelism. There are two known FPGA implementations of local thresholding algorithms: by Jin et al (2009) and Gorgon and Tadeusiewicz (2000). In the first one a simplified version of the LT algorithm, which is a part of an passive auto-focusing system, was implemented in the FPGA.…”
Section: Implementing Local Thresholding In Mitrion-cmentioning
confidence: 99%
“…Jin devised a hardware accelerator linking a camera with a framegrabber. The hardware accelerator was constructed using a field-programmable gate-array (FPGA) which lowered the computational load on the PC [8] but the hardware cost was relatively high because of various connection interfaces. Thus, the hardware approach is inconvenient for supporting the diverse formulations of DFIs.…”
Section: Introductionmentioning
confidence: 99%