2008 42nd Asilomar Conference on Signals, Systems and Computers 2008
DOI: 10.1109/acssc.2008.5074737
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A decimal fully parallel and pipelined floating point multiplier

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Cited by 14 publications
(9 citation statements)
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“…We will focus our attention here on designs using the conventional paradigm of CMOS digital gates although some alternative technologies [8,9] were also considered for decimal circuits at different points in time. Commercial hardware designs for decimal floating point additions were pioneered by IBM [10][11][12], followed by SilMinds [6,[13][14][15], then Fujitsu [16]. All of these commercial implementations use DPD.…”
Section: Specific Designsmentioning
confidence: 99%
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“…We will focus our attention here on designs using the conventional paradigm of CMOS digital gates although some alternative technologies [8,9] were also considered for decimal circuits at different points in time. Commercial hardware designs for decimal floating point additions were pioneered by IBM [10][11][12], followed by SilMinds [6,[13][14][15], then Fujitsu [16]. All of these commercial implementations use DPD.…”
Section: Specific Designsmentioning
confidence: 99%
“…DPD designs started first by presenting ideas for carry-save addition for decimal fixed point multipliers [37] then iterative high-frequency multipliers [38] and multioperand addition [39]. That early work combined with partial product generation [40] formed the base for the complete floating point multipliers [41,42] and the innovative ideas [33] relying on the various decimal codes yielding fully parallel floating point multipliers [13,34].…”
Section: Specific Designsmentioning
confidence: 99%
See 1 more Smart Citation
“…First, the logarithm results are achieved by accumulating the n-digits rounding values of −log 10 (1 + e j 10 −j ) from the 1 st to the k th iteration. In each iteration, the maximum rounding error of −log 10 (1 + e j 10 −j ) is 0.5 × 10 −n therefore the maximum ε q1 is: Table (LUT) for e j ∈ [− 9,9] followed by a shifter to achieve the multiplication by 10 −j , the maximum rounding error of −ej 10 −j ln (10) is 0.5 × 10 −n therefore the maximum ε q2 is:…”
Section: ) Error Analysis: A) Inherent Error Of Algorithmmentioning
confidence: 99%
“…The block diagrams illustrating the architecture of stage 1 and stage 2 are shown in figure(1) and figure(2) respectively. The used Multiplier and CPA are both implemented based on [9] [10]. In the first stage, a multiplier by one digit using Signed Digit (SD) recoding for e j+1 produces two partial products.…”
Section: ) Error Analysis: A) Inherent Error Of Algorithmmentioning
confidence: 99%